View KFG1G16Q2C_1796010.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

onenand1gb(KFG1G16Q2C-xebx) flash memory - 1 - KFG1G16Q2C 1gb onenand c-die * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. onenand ? ? is a trademark of samsung electronics company, ltd. other names and brands may be claimed as the property of their rightful owners.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 2 - revision history document title onenand revision history revision no. history draft date remark 0.0 1.0 1.1 1. initial issue. 1. chapter 1.0 introduction revised. 2. chapter 1.2 ordering information revised. 3. chapter 1.4 product features revised. 4. chapter 3.3.1 cold reset mode operation revised. 5. chapter 6.15 cold reset timing revised. 1. corrected errata. 2. chapter 2.8.18 command register f220h (r/w) revised. 3. chpater 3.4.3 nand array write protection states revised. 4. chapter 3.4.3.1 unlocked nand array write protection state revised. 5. chapter 3.4.3.3 locked-tight nand array write protection state revised. 6. chapter 3.4.4 all block unlock flow diagram revised. 7. chapter 3.13.3 multi-block er ase verify read operation revised. 8. chapter 5.7 ac characteristics for asynchronous write revised. 9. chapter 5.9 ac characteristics for load / program / erase performance revised. apr. 30, 2008 oct. 10. 2008 dec. 16, 2008 advanced final final
onenand1gb(KFG1G16Q2C-xebx) flash memory - 3 - 1.0 introduction this specification contains information about the samsung electronics company onenand ? ? flash memory product family. section 1.0 includes a general overview, revision hist ory, and product ordering information. section 2.0 describes the onenand device. se ction 3.0 provides information about device operation. electrical specifications an d timing waveforms are in sections 4.0 through 6.0. section 7.0 provi des additional application and techni cal notes pertaining to use of the onenand. package dimensions are found in section 8.0. 1.1 flash product type selector samsung offers a variety of flash solu tions including nand flash, onenand ? and nor flash. samsung offers flash products both compo- nent and a variety of card formats including rs-mmc, mmc, compactflash, and smartmedia. to determine which samsung flash product solution is best fo r your application, refer the product selector chart. density part no. v cc (core & io) temperature pkg 1gb KFG1G16Q2C-xebx 1.8v(1.7v~1.95v) extended 63fbga application requires samsung flash products nand onenand ? nor fast random read ? fast sequential read ?? fast write/program ?? multi block erase ? (max 64 blocks) ? erase suspend/resume ?? copyback ? (edc) ? (ecc) lock/unlock/lock-tight ?? ecc external (hardware/software) internal x scalability ??
onenand1gb(KFG1G16Q2C-xebx) flash memory - 4 - 1.2 ordering information 1.3 architectural benefits onenand is a highly integrated non-volatile memory solution based around a nand flash memory array. the chip integrates system features including: ? a bootram and bootloader ? two independent bi-directional 2kb dataram buffers ? a high-speed x16 host interface ? on-chip error correction ? on-chip nor interface controller this on-chip integration enables system des igners to reduce external system logic a nd use high-density nand flash in applicatio ns that would otherwise have to use more nor components. onenand takes advantage of the higher performance nand program ti me, low power, and high density and combines it with the synch ro- nous read performance of nor. the nor flash host interface makes o nenand an ideal solution for appl ications like g3 smart phone s, camera phones, and mobile applications that have large, advance d multimedia applications and operat ing systems, but lack a nand control- ler. when integrated into a samsung multi-chip-package with samsung mobi le ddr sdram, designers can complete a high-performance, sma ll footprint solution. kf g 1g 16 q 2 c - x e x x samsung onenand memory device type g : single chip density 1g : 1gb operating temperature range e : extended temp. (-30 c to 85 c) page architecture 2 : 2kb page version c : 4th generation product line designator b : include bad block d : daisy sample operating voltage range q : 1.8v(1.7 v to 1.95v) package d : fbga(lead free) a : fbga(halogen free) organization 16 : x16 organization speed 6 : 66mhz 8 : 83mhz
onenand1gb(KFG1G16Q2C-xebx) flash memory - 5 - 1.4 product features device architecture ? design technology: ? supply voltage: ? host interface: ? 5kb internal bufferram: ? slc nand array: device performance ? host interface type: ? programmable burst read latency: ? multiple sector read/write: ? multiple reset modes: ? multi block erase: ? low power dissipation: ? reliability system hardware ? voltage detector generating internal reset signal from vcc ? hardware reset input (rp ) ? data protection modes ? user-controlled one time programmable(otp) area ? internal 2bit edc / 1bit ecc ? internal bootloader supports booting solution in system ? handshaking feature ? detailed chip information packaging ? 1gb products c die 1.8v (1.7v ~ 1.95v) 16 bit 1kb bootram, 4kb dataram (2k+64)b page size, (128k+4k)b block size synchronous burst read - up to 66mhz / 83mhz clock frequency - linear burst 4-, 8-, 16-, 32-words with wrap around - continuous 1k words sequential burst synchronous burst block read - up to 66mhz / 83mhz clock frequency - linear burst 4-, 8-, 16-, 32-, 1k-words with no-wrap - continuous (1k words) 64 page sequential burst synchronous write - up to 66mhz / 83mhz clock frequency - linear burst 4-, 8-, 16-, 32-, 1k-words with wrap around - continuous 1k words sequential burst asynchronous random read - 76ns access time asynchronous random write latency 3,4(default),5,6 and 7. 1~40mhz : latency 3 available 1~66mhz : latency 4,5,6 and 7 available over 66mhz : latency 6,7 available. up to 4 sectors using sector count register cold/warm/hot/nand flash core reset up to 64 blocks typical power, - standby current : 10ua - synchronous burst read current(66/83mhz) : 15/20ma - synchronous burst write current(66/83mhz) : 15/20ma - load current : 30ma - program current : 25ma - erase current : 20ma - multi block erase current : 20ma - data retention 10year after 10k program/erase cycles - data retention 1 year after 100k program/erase cycles - write protection for bootram - write protection for nand flash array - write protection during power-up - write protection during power-down - 1st block otp - int pin indicates ready / busy - polling the interrupt register status bit - by id register 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch fbga
onenand1gb(KFG1G16Q2C-xebx) flash memory - 6 - 1.5 general overview onenand ? ? is a monolithic integrated circuit with a nand flash array usi ng a nor flash interface. this device includes c ontrol logic, a nand flash array, and 5kb of internal bufferram. the bufferram reserves 1kb for boot code buffering (bootram) and 4kb for data buffer- ing (dataram), split between 2 independent buffers. it has a x16 ho st interface and a random access time speed of ~76ns. the device operates up to a maximum host-driven clock frequency of 66mhz / 83mhz for synchronous re ads at vcc(or vccq. refer to chapter 4.2) with minimum 6-clock latency. below 40m hz it is accessible with minimum 3-clock latency. appropriate wait cycles are dete rmined by programmable read latency. onenand provides for multiple sector read operations by assigning the number of sector s to be read in the sector counter regist er. the device includes one block-sized otp (one time programmable) area and user-controlled 1st block otp(block 0) that can be used to increase system security or to pr ovide identification capabilities. the attached datasheets are prepared and approved by samsung elec tronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electron ics will evaluate and reply to your re quests and questions about device. if you have any ques- tions, please contact the sams ung branch office near you.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 7 - 2.0 device description 2.1 detailed product description the onenand is an advanced generation, hi gh-performance nand-based flash memory. it integrates on-chip a single-level-cell (slc) nand flash array memory with two independent data buffers, boot ram buffer, a p age buffer for the flash array, and a one-time-programmable block. the combination of these memory areas enabl e high-speed pipelining of reads from host , bufferram , page buffer , and nand flash array. clock speeds up to 66mhz / 83mhz with a x 16 wide i/o yields a 108mbyte/second bandwidth. the onenand also includes a boot ram and boot loader. this enabl es the device to efficiently l oad boot code at device startup f rom the nand array without the need for off-chip boot device. one block of the nand array is set aside as an otp memory area, and 1st block (block 0) can be us ed as otp area. this area, ava ilable to the user, can be configured and lock ed with secured user information. on-chip controller interfaces enable the device to operate in systems without nand host controllers.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 8 - 2.2 definitions b (capital letter) byte, 8bits w (capital letter) word, 16bits b (lower-case letter) bit ecc error correction code calculated ecc ecc that has been calculated during a load or program access written ecc ecc that has been stored as data in the nand flash array or in the bufferram bufferram on-chip internal buffer consisting of bootram and dataram bootram a 1kb portion of the bufferram reserved for boot code buffering dataram a 4kb portion of the bufferram reserved for data buffering sector part of a page of which 512b is the main data area and 16b is the spare data area. it is also the minimum load/pr ogram/copy-back program unit during a 1~4 sector operation is available. data unit possible data unit to be read from memory to bufferram or to be programmed to memory. - 528b of which 512b is in main area and 16b in spare area - 1056b of which 1024b is in main area and 32b in spare area - 1584b of which 1536b is in main area and 48b in spare area - 2112b of which 2048b is in main area and 64b in spare area
onenand1gb(KFG1G16Q2C-xebx) flash memory - 9 - 2.3 pin configuration 2.3.1 1gb product (KFG1G16Q2C) (top view, balls facing down) 63ball fbga onenand chip 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch fbga nc nc nc nc int a0 a1 nc a10 a6 nc nc nc we rp dq14 v ss v ss dq13 dq12 dq8 dq1 oe dq9 v cc dq7 dq4 dq11 dq10 dq3 v cc dq15 a12 dq0 dq5 dq6 ce dq2 nc nc a9 avd a7 a11 a8 a4 a5 a2 a3 nc nc nc nc nc nc nc nc nc core io clk a15 a13 a14 rdy
onenand1gb(KFG1G16Q2C-xebx) flash memory - 10 - 2.4 pin description note : do not leave power supply(vcc-core/vcc-io, v ss ) disconnected. pin name type nameand description host interface a15~a0 i address inputs - inputs for addresses during read and write operation, which are for addressing bufferram & register. dq15~dq0 i/o data inputs/outputs - inputs data during program and commands for all operations, outputs data during memory array/ register read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. int o interrupt notifies the host when a command is completed. after power-up, it is at hi-z condition. once iobe is set to 1, it does not floa t to hi-z condition even when ce is disabled or oe is disabled. rdy o ready indicates data valid in synchronous read modes and is activated while ce is low clk i clock clk synchronizes the device to the system bus frequency in synchronous read mode. the first rising edge of clk in conjunction with avd low latches address input. we i write enable we controls writes to the bufferram and registers. datas are latched on the we pulse?s rising edge avd i address valid detect iindicates valid address presence on address inputs. during asynchronous read operation, all addresses are valid while avd is low, and during synchronous read operation, all addresses are latched on clk?s rising edge while avd is held low for one clock cycle. > low : for asynchronous mode, indicates valid address; for bu rst mode, causes starting address to be latched on rising edge on clk > high : device ignores address inputs rp i reset pin when low, rp resets internal operation of onenand. rp status is don?t care during power-up and bootloading. when high, rp level must be equivalent to vcc-io / vccq level. ce i chip enable ce -low activates internal control logic, and ce -high deselects the device, places it in standby state, and places dq in hi-z. oe i output enable oe -low enables the device?s output data buffers during a read cycle. power supply vcc-core / vcc power for onenand core this is the power supply for onenand core. vcc-io / vccq power for onenand i/o this is the power supply for onenand i/o vcc-io / vccq is internally separated from vcc-core / vcc. vss ground for onenand etc. dnu do not use leave it disconnected. these pins are used for testing. nc no connection lead is not internally connected.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 11 - 2.5 block diagram 2.6 memory array organization the onenand architecture integrates several memory areas on a single chip. 2.6.1 internal (nand array) memory organization the on-chip internal memory is a single-level-cell (slc) nand array used for data storage and code. the internal memory is divi ded into a main area and a spare area. main area the main area is the primary memory array. this main area is di vided into blocks of 64 pages. within a block, each page is 2k b and is com- prised of 4 sectors. within a page, each se ctor is 512b and is comprised of 256 words. spare area the spare area is used for invalid block information and ecc stor age. spare area internal memory is associated with correspondi ng main area memory. within a block, each page has four 16b sect ors of spare area. each spare area sector is 8 words. bootram statemachine bootloader internal registers (address/command/configuration /status registers) error correction logic dataram0 bufferram nand flash array otp (one block) dataram1 1st block otp host interface clk oe we rp avd int rdy a15~a0 dq15~dq0 ce (block 0)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 12 - internal memory array information internal memory array organization area block page sector main 128kb 2kb 512b spare 4kb 64b 16b 2kb page0 512b 16b 64b page0 2kb page63 64b page63 sector main area spare area block page main area spare area 2kb 64b main area spare area 128kb 4kb page 0 page 63 512b sector0 512b sector1 512b sector2 512b sector3 16b sector0 16b sector1 16b sector2 16b sector3
onenand1gb(KFG1G16Q2C-xebx) flash memory - 13 - 2.6.2 external (bufferram) memory organization the on-chip external memory is comprised of 3 buffers used for boot code storage and data buffering. the bootram is a 1kb buffer that receives boot code from the internal memory and makes it available to the host at start up. there are two independent 2kb bi-directional data buffers, datara m0 and dataram1. these dual buffers enable the host to execute simul- taneous read-while load, and write-while-program operations after bo ot up. during boot up, the bootram is used by the host to i nitialize the main memory, and deliver boot code from nand flash core to host. the external memory is divided into a main area and a spar e area. each buffer is the equivalent size of a sector. the main area data is 512b. the spare area data is 16b. external memory array information area bootram dataram0 dataram1 total size 1kb+32b 2kb+64b 2kb+64b number of sectors 2 4 4 sector main 512b 512b 512b spare 16b 16b 16b host otp block nand array boot code (1kb) bootram (1kb) dataram0 (2kb) dataram1 (2kb) external (bufferram) memory internal (nand array) memory
onenand1gb(KFG1G16Q2C-xebx) flash memory - 14 - external memory array organization bootram 0 bootram 1 bootram dataram 1_0 dataram 1_1 dataram 1_2 dataram 1_3 dataram1 { main area data spare area data dataram 0_0 dataram 0_1 dataram 0_2 dataram 0_3 dataram0 sector: (512 + 16) byte { (512b) (16b)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 15 - 2.7 memory map the following tables are the memory maps for the onenand. 2.7.1 internal (nand array) memory organization the following tables show the internal memory address map in word order. block block address page and sector address size block block address page and sector address size block0 0000h 0000h~00ffh 128kb block32 0020h 0000h~00ffh 128kb block1 0001h 0000h~00ffh 128kb block33 0021h 0000h~00ffh 128kb block2 0002h 0000h~00ffh 128kb block34 0022h 0000h~00ffh 128kb block3 0003h 0000h~00ffh 128kb block35 0023h 0000h~00ffh 128kb block4 0004h 0000h~00ffh 128kb block36 0024h 0000h~00ffh 128kb block5 0005h 0000h~00ffh 128kb block37 0025h 0000h~00ffh 128kb block6 0006h 0000h~00ffh 128kb block38 0026h 0000h~00ffh 128kb block7 0007h 0000h~00ffh 128kb block39 0027h 0000h~00ffh 128kb block8 0008h 0000h~00ffh 128kb block40 0028h 0000h~00ffh 128kb block9 0009h 0000h~00ffh 128kb block41 0029h 0000h~00ffh 128kb block10 000ah 0000h~00ffh 128kb block42 002ah 0000h~00ffh 128kb block11 000bh 0000h~00ffh 128kb block43 002bh 0000h~00ffh 128kb block12 000ch 0000h~00ffh 128kb block44 002ch 0000h~00ffh 128kb block13 000dh 0000h~00ffh 128kb block45 002dh 0000h~00ffh 128kb block14 000eh 0000h~00ffh 128kb block46 002eh 0000h~00ffh 128kb block15 000fh 0000h~00ffh 128kb block47 002fh 0000h~00ffh 128kb block16 0010h 0000h~00ffh 128kb block48 0030h 0000h~00ffh 128kb block17 0011h 0000h~00ffh 128kb block49 0031h 0000h~00ffh 128kb block18 0012h 0000h~00ffh 128kb block50 0032h 0000h~00ffh 128kb block19 0013h 0000h~00ffh 128kb block51 0033h 0000h~00ffh 128kb block20 0014h 0000h~00ffh 128kb block52 0034h 0000h~00ffh 128kb block21 0015h 0000h~00ffh 128kb block53 0035h 0000h~00ffh 128kb block22 0016h 0000h~00ffh 128kb block54 0036h 0000h~00ffh 128kb block23 0017h 0000h~00ffh 128kb block55 0037h 0000h~00ffh 128kb block24 0018h 0000h~00ffh 128kb block56 0038h 0000h~00ffh 128kb block25 0019h 0000h~00ffh 128kb block57 0039h 0000h~00ffh 128kb block26 001ah 0000h~00ffh 128kb block58 003ah 0000h~00ffh 128kb block27 001bh 0000h~00ffh 128kb block59 003bh 0000h~00ffh 128kb block28 001ch 0000h~00ffh 128kb block60 003ch 0000h~00ffh 128kb block29 001dh 0000h~00ffh 128kb block61 003dh 0000h~00ffh 128kb block30 001eh 0000h~00ffh 128kb block62 003eh 0000h~00ffh 128kb block31 001fh 0000h~00ffh 128kb block63 003fh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 16 - block block address page and sector address size block block address page and sector address size block64 0040h 0000h~00ffh 128kb block96 0060h 0000h~00ffh 128kb block65 0041h 0000h~00ffh 128kb block97 0061h 0000h~00ffh 128kb block66 0042h 0000h~00ffh 128kb block98 0062h 0000h~00ffh 128kb block67 0043h 0000h~00ffh 128kb block99 0063h 0000h~00ffh 128kb block68 0044h 0000h~00ffh 128kb block100 0064h 0000h~00ffh 128kb block69 0045h 0000h~00ffh 128kb block101 0065h 0000h~00ffh 128kb block70 0046h 0000h~00ffh 128kb block102 0066h 0000h~00ffh 128kb block71 0047h 0000h~00ffh 128kb block103 0067h 0000h~00ffh 128kb block72 0048h 0000h~00ffh 128kb block104 0068h 0000h~00ffh 128kb block73 0049h 0000h~00ffh 128kb block105 0069h 0000h~00ffh 128kb block74 004ah 0000h~00ffh 128kb block106 006ah 0000h~00ffh 128kb block75 004bh 0000h~00ffh 128kb block107 006bh 0000h~00ffh 128kb block76 004ch 0000h~00ffh 128kb block108 006ch 0000h~00ffh 128kb block77 004dh 0000h~00ffh 128kb block109 006dh 0000h~00ffh 128kb block78 004eh 0000h~00ffh 128kb block110 006eh 0000h~00ffh 128kb block79 004fh 0000h~00ffh 128kb block111 006fh 0000h~00ffh 128kb block80 0050h 0000h~00ffh 128kb block112 0070h 0000h~00ffh 128kb block81 0051h 0000h~00ffh 128kb block113 0071h 0000h~00ffh 128kb block82 0052h 0000h~00ffh 128kb block114 0072h 0000h~00ffh 128kb block83 0053h 0000h~00ffh 128kb block115 0073h 0000h~00ffh 128kb block84 0054h 0000h~00ffh 128kb block116 0074h 0000h~00ffh 128kb block85 0055h 0000h~00ffh 128kb block117 0075h 0000h~00ffh 128kb block86 0056h 0000h~00ffh 128kb block118 0076h 0000h~00ffh 128kb block87 0057h 0000h~00ffh 128kb block119 0077h 0000h~00ffh 128kb block88 0058h 0000h~00ffh 128kb block120 0078h 0000h~00ffh 128kb block89 0059h 0000h~00ffh 128kb block121 0079h 0000h~00ffh 128kb block90 005ah 0000h~00ffh 128kb block122 007ah 0000h~00ffh 128kb block91 005bh 0000h~00ffh 128kb block123 007bh 0000h~00ffh 128kb block92 005ch 0000h~00ffh 128kb block124 007ch 0000h~00ffh 128kb block93 005dh 0000h~00ffh 128kb block125 007dh 0000h~00ffh 128kb block94 005eh 0000h~00ffh 128kb block126 007eh 0000h~00ffh 128kb block95 005fh 0000h~00ffh 128kb block127 007fh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 17 - block block address page and sector address size block block address page and sector address size block128 0080h 0000h~00ffh 128kb block160 00a0h 0000h~00ffh 128kb block129 0081h 0000h~00ffh 128kb block161 00a1h 0000h~00ffh 128kb block130 0082h 0000h~00ffh 128kb block162 00a2h 0000h~00ffh 128kb block131 0083h 0000h~00ffh 128kb block163 00a3h 0000h~00ffh 128kb block132 0084h 0000h~00ffh 128kb block164 00a4h 0000h~00ffh 128kb block133 0085h 0000h~00ffh 128kb block165 00a5h 0000h~00ffh 128kb block134 0086h 0000h~00ffh 128kb block166 00a6h 0000h~00ffh 128kb block135 0087h 0000h~00ffh 128kb block167 00a7h 0000h~00ffh 128kb block136 0088h 0000h~00ffh 128kb block168 00a8h 0000h~00ffh 128kb block137 0089h 0000h~00ffh 128kb block169 00a9h 0000h~00ffh 128kb block138 008ah 0000h~00ffh 128kb block170 00aah 0000h~00ffh 128kb block139 008bh 0000h~00ffh 128kb block171 00abh 0000h~00ffh 128kb block140 008ch 0000h~00ffh 128kb block172 00ach 0000h~00ffh 128kb block141 008dh 0000h~00ffh 128kb block173 00adh 0000h~00ffh 128kb block142 008eh 0000h~00ffh 128kb block174 00aeh 0000h~00ffh 128kb block143 008fh 0000h~00ffh 128kb block175 00afh 0000h~00ffh 128kb block144 0090h 0000h~00ffh 128kb block176 00b0h 0000h~00ffh 128kb block145 0091h 0000h~00ffh 128kb block177 00b1h 0000h~00ffh 128kb block146 0092h 0000h~00ffh 128kb block178 00b2h 0000h~00ffh 128kb block147 0093h 0000h~00ffh 128kb block179 00b3h 0000h~00ffh 128kb block148 0094h 0000h~00ffh 128kb block180 00b4h 0000h~00ffh 128kb block149 0095h 0000h~00ffh 128kb block181 00b5h 0000h~00ffh 128kb block150 0096h 0000h~00ffh 128kb block182 00b6h 0000h~00ffh 128kb block151 0097h 0000h~00ffh 128kb block183 00b7h 0000h~00ffh 128kb block152 0098h 0000h~00ffh 128kb block184 00b8h 0000h~00ffh 128kb block153 0099h 0000h~00ffh 128kb block185 00b9h 0000h~00ffh 128kb block154 009ah 0000h~00ffh 128kb block186 00bah 0000h~00ffh 128kb block155 009bh 0000h~00ffh 128kb block187 00bbh 0000h~00ffh 128kb block156 009ch 0000h~00ffh 128kb block188 00bch 0000h~00ffh 128kb block157 009dh 0000h~00ffh 128kb block189 00bdh 0000h~00ffh 128kb block158 009eh 0000h~00ffh 128kb block190 00beh 0000h~00ffh 128kb block159 009fh 0000h~00ffh 128kb block191 00bfh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 18 - block block address page and sector address size block block address page and sector address size block192 00c0h 0000h~00ffh 128kb block224 00e0h 0000h~00ffh 128kb block193 00c1h 0000h~00ffh 128kb block225 00e1h 0000h~00ffh 128kb block194 00c2h 0000h~00ffh 128kb block226 00e2h 0000h~00ffh 128kb block195 00c3h 0000h~00ffh 128kb block227 00e3h 0000h~00ffh 128kb block196 00c4h 0000h~00ffh 128kb block228 00e4h 0000h~00ffh 128kb block197 00c5h 0000h~00ffh 128kb block229 00e5h 0000h~00ffh 128kb block198 00c6h 0000h~00ffh 128kb block230 00e6h 0000h~00ffh 128kb block199 00c7h 0000h~00ffh 128kb block231 00e7h 0000h~00ffh 128kb block200 00c8h 0000h~00ffh 128kb block232 00e8h 0000h~00ffh 128kb block201 00c9h 0000h~00ffh 128kb block233 00e9h 0000h~00ffh 128kb block202 00cah 0000h~00ffh 128kb block234 00eah 0000h~00ffh 128kb block203 00cbh 0000h~00ffh 128kb block235 00ebh 0000h~00ffh 128kb block204 00cch 0000h~00ffh 128kb block236 00ech 0000h~00ffh 128kb block205 00cdh 0000h~00ffh 128kb block237 00edh 0000h~00ffh 128kb block206 00ceh 0000h~00ffh 128kb block238 00eeh 0000h~00ffh 128kb block207 00cfh 0000h~00ffh 128kb block239 00efh 0000h~00ffh 128kb block208 00d0h 0000h~00ffh 128kb block240 00f0h 0000h~00ffh 128kb block209 00d1h 0000h~00ffh 128kb block241 00f1h 0000h~00ffh 128kb block210 00d2h 0000h~00ffh 128kb block242 00f2h 0000h~00ffh 128kb block211 00d3h 0000h~00ffh 128kb block243 00f3h 0000h~00ffh 128kb block212 00d4h 0000h~00ffh 128kb block244 00f4h 0000h~00ffh 128kb block213 00d5h 0000h~00ffh 128kb block245 00f5h 0000h~00ffh 128kb block214 00d6h 0000h~00ffh 128kb block246 00f6h 0000h~00ffh 128kb block215 00d7h 0000h~00ffh 128kb block247 00f7h 0000h~00ffh 128kb block216 00d8h 0000h~00ffh 128kb block248 00f8h 0000h~00ffh 128kb block217 00d9h 0000h~00ffh 128kb block249 00f9h 0000h~00ffh 128kb block218 00dah 0000h~00ffh 128kb block250 00fah 0000h~00ffh 128kb block219 00dbh 0000h~00ffh 128kb block251 00fbh 0000h~00ffh 128kb block220 00dch 0000h~00ffh 128kb block252 00fch 0000h~00ffh 128kb block221 00ddh 0000h~00ffh 128kb block253 00fdh 0000h~00ffh 128kb block222 00deh 0000h~00ffh 128kb block254 00feh 0000h~00ffh 128kb block223 00dfh 0000h~00ffh 128kb block255 00ffh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 19 - block block address page and sector address size block block address page and sector address size block256 0100h 0000h~00ffh 128kb block288 0120h 0000h~00ffh 128kb block257 0101h 0000h~00ffh 128kb block289 0121h 0000h~00ffh 128kb block258 0102h 0000h~00ffh 128kb block290 0122h 0000h~00ffh 128kb block259 0103h 0000h~00ffh 128kb block291 0123h 0000h~00ffh 128kb block260 0104h 0000h~00ffh 128kb block292 0124h 0000h~00ffh 128kb block261 0105h 0000h~00ffh 128kb block293 0125h 0000h~00ffh 128kb block262 0106h 0000h~00ffh 128kb block294 0126h 0000h~00ffh 128kb block263 0107h 0000h~00ffh 128kb block295 0127h 0000h~00ffh 128kb block264 0108h 0000h~00ffh 128kb block296 0128h 0000h~00ffh 128kb block265 0109h 0000h~00ffh 128kb block297 0129h 0000h~00ffh 128kb block266 010ah 0000h~00ffh 128kb block298 012ah 0000h~00ffh 128kb block267 010bh 0000h~00ffh 128kb block299 012bh 0000h~00ffh 128kb block268 010ch 0000h~00ffh 128kb block300 012ch 0000h~00ffh 128kb block269 010dh 0000h~00ffh 128kb block301 012dh 0000h~00ffh 128kb block270 010eh 0000h~00ffh 128kb block302 012eh 0000h~00ffh 128kb block271 010fh 0000h~00ffh 128kb block303 012fh 0000h~00ffh 128kb block272 0110h 0000h~00ffh 128kb block304 0130h 0000h~00ffh 128kb block273 0111h 0000h~00ffh 128kb block305 0131h 0000h~00ffh 128kb block274 0112h 0000h~00ffh 128kb block306 0132h 0000h~00ffh 128kb block275 0113h 0000h~00ffh 128kb block307 0133h 0000h~00ffh 128kb block276 0114h 0000h~00ffh 128kb block308 0134h 0000h~00ffh 128kb block277 0115h 0000h~00ffh 128kb block309 0135h 0000h~00ffh 128kb block278 0116h 0000h~00ffh 128kb block310 0136h 0000h~00ffh 128kb block279 0117h 0000h~00ffh 128kb block311 0137h 0000h~00ffh 128kb block280 0118h 0000h~00ffh 128kb block312 0138h 0000h~00ffh 128kb block281 0119h 0000h~00ffh 128kb block313 0139h 0000h~00ffh 128kb block282 011ah 0000h~00ffh 128kb block314 013ah 0000h~00ffh 128kb block283 011bh 0000h~00ffh 128kb block315 013bh 0000h~00ffh 128kb block284 011ch 0000h~00ffh 128kb block316 013ch 0000h~00ffh 128kb block285 011dh 0000h~00ffh 128kb block317 013dh 0000h~00ffh 128kb block286 011eh 0000h~00ffh 128kb block318 013eh 0000h~00ffh 128kb block287 011fh 0000h~00ffh 128kb block319 013fh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 20 - block block address page and sector address size block block address page and sector address size block320 0140h 0000h~00ffh 128kb block352 0160h 0000h~00ffh 128kb block321 0141h 0000h~00ffh 128kb block353 0161h 0000h~00ffh 128kb block322 0142h 0000h~00ffh 128kb block354 0162h 0000h~00ffh 128kb block323 0143h 0000h~00ffh 128kb block355 0163h 0000h~00ffh 128kb block324 0144h 0000h~00ffh 128kb block356 0164h 0000h~00ffh 128kb block325 0145h 0000h~00ffh 128kb block357 0165h 0000h~00ffh 128kb block326 0146h 0000h~00ffh 128kb block358 0166h 0000h~00ffh 128kb block327 0147h 0000h~00ffh 128kb block359 0167h 0000h~00ffh 128kb block328 0148h 0000h~00ffh 128kb block360 0168h 0000h~00ffh 128kb block329 0149h 0000h~00ffh 128kb block361 0169h 0000h~00ffh 128kb block330 014ah 0000h~00ffh 128kb block362 016ah 0000h~00ffh 128kb block331 014bh 0000h~00ffh 128kb block363 016bh 0000h~00ffh 128kb block332 014ch 0000h~00ffh 128kb block364 016ch 0000h~00ffh 128kb block333 014dh 0000h~00ffh 128kb block365 016dh 0000h~00ffh 128kb block334 014eh 0000h~00ffh 128kb block366 016eh 0000h~00ffh 128kb block335 014fh 0000h~00ffh 128kb block367 016fh 0000h~00ffh 128kb block336 0150h 0000h~00ffh 128kb block368 0170h 0000h~00ffh 128kb block337 0151h 0000h~00ffh 128kb block369 0171h 0000h~00ffh 128kb block338 0152h 0000h~00ffh 128kb block370 0172h 0000h~00ffh 128kb block339 0153h 0000h~00ffh 128kb block371 0173h 0000h~00ffh 128kb block340 0154h 0000h~00ffh 128kb block372 0174h 0000h~00ffh 128kb block341 0155h 0000h~00ffh 128kb block373 0175h 0000h~00ffh 128kb block342 0156h 0000h~00ffh 128kb block374 0176h 0000h~00ffh 128kb block343 0157h 0000h~00ffh 128kb block375 0177h 0000h~00ffh 128kb block344 0158h 0000h~00ffh 128kb block376 0178h 0000h~00ffh 128kb block345 0159h 0000h~00ffh 128kb block377 0179h 0000h~00ffh 128kb block346 015ah 0000h~00ffh 128kb block378 017ah 0000h~00ffh 128kb block347 015bh 0000h~00ffh 128kb block379 017bh 0000h~00ffh 128kb block348 015ch 0000h~00ffh 128kb block380 017ch 0000h~00ffh 128kb block349 015dh 0000h~00ffh 128kb block381 017dh 0000h~00ffh 128kb block350 015eh 0000h~00ffh 128kb block382 017eh 0000h~00ffh 128kb block351 015fh 0000h~00ffh 128kb block383 017fh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 21 - block block address page and sector address size block block address page and sector address size block384 0180h 0000h~00ffh 128kb block416 01a0h 0000h~00ffh 128kb block385 0181h 0000h~00ffh 128kb block417 01a1h 0000h~00ffh 128kb block386 0182h 0000h~00ffh 128kb block418 01a2h 0000h~00ffh 128kb block387 0183h 0000h~00ffh 128kb block419 01a3h 0000h~00ffh 128kb block388 0184h 0000h~00ffh 128kb block420 01a4h 0000h~00ffh 128kb block389 0185h 0000h~00ffh 128kb block421 01a5h 0000h~00ffh 128kb block390 0186h 0000h~00ffh 128kb block422 01a6h 0000h~00ffh 128kb block391 0187h 0000h~00ffh 128kb block423 01a7h 0000h~00ffh 128kb block392 0188h 0000h~00ffh 128kb block424 01a8h 0000h~00ffh 128kb block393 0189h 0000h~00ffh 128kb block425 01a9h 0000h~00ffh 128kb block394 018ah 0000h~00ffh 128kb block426 01aah 0000h~00ffh 128kb block395 018bh 0000h~00ffh 128kb block427 01abh 0000h~00ffh 128kb block396 018ch 0000h~00ffh 128kb block428 01ach 0000h~00ffh 128kb block397 018dh 0000h~00ffh 128kb block429 01adh 0000h~00ffh 128kb block398 018eh 0000h~00ffh 128kb block430 01aeh 0000h~00ffh 128kb block399 018fh 0000h~00ffh 128kb block431 01afh 0000h~00ffh 128kb block400 0190h 0000h~00ffh 128kb block432 01b0h 0000h~00ffh 128kb block401 0191h 0000h~00ffh 128kb block433 01b1h 0000h~00ffh 128kb block402 0192h 0000h~00ffh 128kb block434 01b2h 0000h~00ffh 128kb block403 0193h 0000h~00ffh 128kb block435 01b3h 0000h~00ffh 128kb block404 0194h 0000h~00ffh 128kb block436 01b4h 0000h~00ffh 128kb block405 0195h 0000h~00ffh 128kb block437 01b5h 0000h~00ffh 128kb block406 0196h 0000h~00ffh 128kb block438 01b6h 0000h~00ffh 128kb block407 0197h 0000h~00ffh 128kb block439 01b7h 0000h~00ffh 128kb block408 0198h 0000h~00ffh 128kb block440 01b8h 0000h~00ffh 128kb block409 0199h 0000h~00ffh 128kb block441 01b9h 0000h~00ffh 128kb block410 019ah 0000h~00ffh 128kb block442 01bah 0000h~00ffh 128kb block411 019bh 0000h~00ffh 128kb block443 01bbh 0000h~00ffh 128kb block412 019ch 0000h~00ffh 128kb block444 01bch 0000h~00ffh 128kb block413 019dh 0000h~00ffh 128kb block445 01bdh 0000h~00ffh 128kb block414 019eh 0000h~00ffh 128kb block446 01beh 0000h~00ffh 128kb block415 019fh 0000h~00ffh 128kb block447 01bfh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 22 - block block address page and sector address size block block address page and sector address size block448 01c0h 0000h~00ffh 128kb block480 01e0h 0000h~00ffh 128kb block449 01c1h 0000h~00ffh 128kb block481 01e1h 0000h~00ffh 128kb block450 01c2h 0000h~00ffh 128kb block482 01e2h 0000h~00ffh 128kb block451 01c3h 0000h~00ffh 128kb block483 01e3h 0000h~00ffh 128kb block452 01c4h 0000h~00ffh 128kb block484 01e4h 0000h~00ffh 128kb block453 01c5h 0000h~00ffh 128kb block485 01e5h 0000h~00ffh 128kb block454 01c6h 0000h~00ffh 128kb block486 01e6h 0000h~00ffh 128kb block455 01c7h 0000h~00ffh 128kb block487 01e7h 0000h~00ffh 128kb block456 01c8h 0000h~00ffh 128kb block488 01e8h 0000h~00ffh 128kb block457 01c9h 0000h~00ffh 128kb block489 01e9h 0000h~00ffh 128kb block458 01cah 0000h~00ffh 128kb block490 01eah 0000h~00ffh 128kb block459 01cbh 0000h~00ffh 128kb block491 01ebh 0000h~00ffh 128kb block460 01cch 0000h~00ffh 128kb block492 01ech 0000h~00ffh 128kb block461 01cdh 0000h~00ffh 128kb block493 01edh 0000h~00ffh 128kb block462 01ceh 0000h~00ffh 128kb block494 01eeh 0000h~00ffh 128kb block463 01cfh 0000h~00ffh 128kb block495 01efh 0000h~00ffh 128kb block464 01d0h 0000h~00ffh 128kb block496 01f0h 0000h~00ffh 128kb block465 01d1h 0000h~00ffh 128kb block497 01f1h 0000h~00ffh 128kb block466 01d2h 0000h~00ffh 128kb block498 01f2h 0000h~00ffh 128kb block467 01d3h 0000h~00ffh 128kb block499 01f3h 0000h~00ffh 128kb block468 01d4h 0000h~00ffh 128kb block500 01f4h 0000h~00ffh 128kb block469 01d5h 0000h~00ffh 128kb block501 01f5h 0000h~00ffh 128kb block470 01d6h 0000h~00ffh 128kb block502 01f6h 0000h~00ffh 128kb block471 01d7h 0000h~00ffh 128kb block503 01f7h 0000h~00ffh 128kb block472 01d8h 0000h~00ffh 128kb block504 01f8h 0000h~00ffh 128kb block473 01d9h 0000h~00ffh 128kb block505 01f9h 0000h~00ffh 128kb block474 01dah 0000h~00ffh 128kb block506 01fah 0000h~00ffh 128kb block475 01dbh 0000h~00ffh 128kb block507 01fbh 0000h~00ffh 128kb block476 01dch 0000h~00ffh 128kb block508 01fch 0000h~00ffh 128kb block477 01ddh 0000h~00ffh 128kb block509 01fdh 0000h~00ffh 128kb block478 01deh 0000h~00ffh 128kb block510 01feh 0000h~00ffh 128kb block479 01dfh 0000h~00ffh 128kb block511 01ffh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 23 - block block address page and sector address size block block address page and sector address size block512 0200h 0000h~00ffh 128kb block544 0220h 0000h~00ffh 128kb block513 0201h 0000h~00ffh 128kb block545 0221h 0000h~00ffh 128kb block514 0202h 0000h~00ffh 128kb block546 0222h 0000h~00ffh 128kb block515 0203h 0000h~00ffh 128kb block547 0223h 0000h~00ffh 128kb block516 0204h 0000h~00ffh 128kb block548 0224h 0000h~00ffh 128kb block517 0205h 0000h~00ffh 128kb block549 0225h 0000h~00ffh 128kb block518 0206h 0000h~00ffh 128kb block550 0226h 0000h~00ffh 128kb block519 0207h 0000h~00ffh 128kb block551 0227h 0000h~00ffh 128kb block520 0208h 0000h~00ffh 128kb block552 0228h 0000h~00ffh 128kb block521 0209h 0000h~00ffh 128kb block553 0229h 0000h~00ffh 128kb block522 020ah 0000h~00ffh 128kb block554 022ah 0000h~00ffh 128kb block523 020bh 0000h~00ffh 128kb block555 022bh 0000h~00ffh 128kb block524 020ch 0000h~00ffh 128kb block556 022ch 0000h~00ffh 128kb block525 020dh 0000h~00ffh 128kb block557 022dh 0000h~00ffh 128kb block526 020eh 0000h~00ffh 128kb block558 022eh 0000h~00ffh 128kb block527 020fh 0000h~00ffh 128kb block559 022fh 0000h~00ffh 128kb block528 0210h 0000h~00ffh 128kb block560 0230h 0000h~00ffh 128kb block529 0211h 0000h~00ffh 128kb block561 0231h 0000h~00ffh 128kb block530 0212h 0000h~00ffh 128kb block562 0232h 0000h~00ffh 128kb block531 0213h 0000h~00ffh 128kb block563 0233h 0000h~00ffh 128kb block532 0214h 0000h~00ffh 128kb block564 0234h 0000h~00ffh 128kb block533 0215h 0000h~00ffh 128kb block565 0235h 0000h~00ffh 128kb block534 0216h 0000h~00ffh 128kb block566 0236h 0000h~00ffh 128kb block535 0217h 0000h~00ffh 128kb block567 0237h 0000h~00ffh 128kb block536 0218h 0000h~00ffh 128kb block568 0238h 0000h~00ffh 128kb block537 0219h 0000h~00ffh 128kb block569 0239h 0000h~00ffh 128kb block538 021ah 0000h~00ffh 128kb block570 023ah 0000h~00ffh 128kb block539 021bh 0000h~00ffh 128kb block571 023bh 0000h~00ffh 128kb block540 021ch 0000h~00ffh 128kb block572 023ch 0000h~00ffh 128kb block541 021dh 0000h~00ffh 128kb block573 023dh 0000h~00ffh 128kb block542 021eh 0000h~00ffh 128kb block574 023eh 0000h~00ffh 128kb block543 021fh 0000h~00ffh 128kb block575 023fh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 24 - block block address page and sector address size block block address page and sector address size block576 0240h 0000h~00ffh 128kb block608 0260h 0000h~00ffh 128kb block577 0241h 0000h~00ffh 128kb block609 0261h 0000h~00ffh 128kb block578 0242h 0000h~00ffh 128kb block610 0262h 0000h~00ffh 128kb block579 0243h 0000h~00ffh 128kb block611 0263h 0000h~00ffh 128kb block580 0244h 0000h~00ffh 128kb block612 0264h 0000h~00ffh 128kb block581 0245h 0000h~00ffh 128kb block613 0265h 0000h~00ffh 128kb block582 0246h 0000h~00ffh 128kb block614 0266h 0000h~00ffh 128kb block583 0247h 0000h~00ffh 128kb block615 0267h 0000h~00ffh 128kb block584 0248h 0000h~00ffh 128kb block616 0268h 0000h~00ffh 128kb block585 0249h 0000h~00ffh 128kb block617 0269h 0000h~00ffh 128kb block586 024ah 0000h~00ffh 128kb block618 026ah 0000h~00ffh 128kb block587 024bh 0000h~00ffh 128kb block619 026bh 0000h~00ffh 128kb block588 024ch 0000h~00ffh 128kb block620 026ch 0000h~00ffh 128kb block589 024dh 0000h~00ffh 128kb block621 026dh 0000h~00ffh 128kb block590 024eh 0000h~00ffh 128kb block622 026eh 0000h~00ffh 128kb block591 024fh 0000h~00ffh 128kb block623 026fh 0000h~00ffh 128kb block592 0250h 0000h~00ffh 128kb block624 0270h 0000h~00ffh 128kb block593 0251h 0000h~00ffh 128kb block625 0271h 0000h~00ffh 128kb block594 0252h 0000h~00ffh 128kb block626 0272h 0000h~00ffh 128kb block595 0253h 0000h~00ffh 128kb block627 0273h 0000h~00ffh 128kb block596 0254h 0000h~00ffh 128kb block628 0274h 0000h~00ffh 128kb block597 0255h 0000h~00ffh 128kb block629 0275h 0000h~00ffh 128kb block598 0256h 0000h~00ffh 128kb block630 0276h 0000h~00ffh 128kb block599 0257h 0000h~00ffh 128kb block631 0277h 0000h~00ffh 128kb block600 0258h 0000h~00ffh 128kb block632 0278h 0000h~00ffh 128kb block601 0259h 0000h~00ffh 128kb block633 0279h 0000h~00ffh 128kb block602 025ah 0000h~00ffh 128kb block634 027ah 0000h~00ffh 128kb block603 025bh 0000h~00ffh 128kb block635 027bh 0000h~00ffh 128kb block604 025ch 0000h~00ffh 128kb block636 027ch 0000h~00ffh 128kb block605 025dh 0000h~00ffh 128kb block637 027dh 0000h~00ffh 128kb block606 025eh 0000h~00ffh 128kb block638 027eh 0000h~00ffh 128kb block607 025fh 0000h~00ffh 128kb block639 027fh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 25 - block block address page and sector address size block block address page and sector address size block640 0280h 0000h~00ffh 128kb block672 02a0h 0000h~00ffh 128kb block641 0281h 0000h~00ffh 128kb block673 02a1h 0000h~00ffh 128kb block642 0282h 0000h~00ffh 128kb block674 02a2h 0000h~00ffh 128kb block643 0283h 0000h~00ffh 128kb block675 02a3h 0000h~00ffh 128kb block644 0284h 0000h~00ffh 128kb block676 02a4h 0000h~00ffh 128kb block645 0285h 0000h~00ffh 128kb block677 02a5h 0000h~00ffh 128kb block646 0286h 0000h~00ffh 128kb block678 02a6h 0000h~00ffh 128kb block647 0287h 0000h~00ffh 128kb block679 02a7h 0000h~00ffh 128kb block648 0288h 0000h~00ffh 128kb block680 02a8h 0000h~00ffh 128kb block649 0289h 0000h~00ffh 128kb block681 02a9h 0000h~00ffh 128kb block650 028ah 0000h~00ffh 128kb block682 02aah 0000h~00ffh 128kb block651 028bh 0000h~00ffh 128kb block683 02abh 0000h~00ffh 128kb block652 028ch 0000h~00ffh 128kb block684 02ach 0000h~00ffh 128kb block653 028dh 0000h~00ffh 128kb block685 02adh 0000h~00ffh 128kb block654 028eh 0000h~00ffh 128kb block686 02aeh 0000h~00ffh 128kb block655 028fh 0000h~00ffh 128kb block687 02afh 0000h~00ffh 128kb block656 0290h 0000h~00ffh 128kb block688 02b0h 0000h~00ffh 128kb block657 0291h 0000h~00ffh 128kb block689 02b1h 0000h~00ffh 128kb block658 0292h 0000h~00ffh 128kb block690 02b2h 0000h~00ffh 128kb block659 0293h 0000h~00ffh 128kb block691 02b3h 0000h~00ffh 128kb block660 0294h 0000h~00ffh 128kb block692 02b4h 0000h~00ffh 128kb block661 0295h 0000h~00ffh 128kb block693 02b5h 0000h~00ffh 128kb block662 0296h 0000h~00ffh 128kb block694 02b6h 0000h~00ffh 128kb block663 0297h 0000h~00ffh 128kb block695 02b7h 0000h~00ffh 128kb block664 0298h 0000h~00ffh 128kb block696 02b8h 0000h~00ffh 128kb block665 0299h 0000h~00ffh 128kb block697 02b9h 0000h~00ffh 128kb block666 029ah 0000h~00ffh 128kb block698 02bah 0000h~00ffh 128kb block667 029bh 0000h~00ffh 128kb block699 02bbh 0000h~00ffh 128kb block668 029ch 0000h~00ffh 128kb block700 02bch 0000h~00ffh 128kb block669 029dh 0000h~00ffh 128kb block701 02bdh 0000h~00ffh 128kb block670 029eh 0000h~00ffh 128kb block702 02beh 0000h~00ffh 128kb block671 029fh 0000h~00ffh 128kb block703 02bfh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 26 - block block address page and sector address size block block address page and sector address size block704 02c0h 0000h~00ffh 128kb block736 02e0h 0000h~00ffh 128kb block705 02c1h 0000h~00ffh 128kb block737 02e1h 0000h~00ffh 128kb block706 02c2h 0000h~00ffh 128kb block738 02e2h 0000h~00ffh 128kb block707 02c3h 0000h~00ffh 128kb block739 02e3h 0000h~00ffh 128kb block708 02c4h 0000h~00ffh 128kb block740 02e4h 0000h~00ffh 128kb block709 02c5h 0000h~00ffh 128kb block741 02e5h 0000h~00ffh 128kb block710 02c6h 0000h~00ffh 128kb block742 02e6h 0000h~00ffh 128kb block711 02c7h 0000h~00ffh 128kb block743 02e7h 0000h~00ffh 128kb block712 02c8h 0000h~00ffh 128kb block744 02e8h 0000h~00ffh 128kb block713 02c9h 0000h~00ffh 128kb block745 02e9h 0000h~00ffh 128kb block714 02cah 0000h~00ffh 128kb block746 02eah 0000h~00ffh 128kb block715 02cbh 0000h~00ffh 128kb block747 02ebh 0000h~00ffh 128kb block716 02cch 0000h~00ffh 128kb block748 02ech 0000h~00ffh 128kb block717 02cdh 0000h~00ffh 128kb block749 02edh 0000h~00ffh 128kb block718 02ceh 0000h~00ffh 128kb block750 02eeh 0000h~00ffh 128kb block719 02cfh 0000h~00ffh 128kb block751 02efh 0000h~00ffh 128kb block720 02d0h 0000h~00ffh 128kb block752 02f0h 0000h~00ffh 128kb block721 02d1h 0000h~00ffh 128kb block753 02f1h 0000h~00ffh 128kb block722 02d2h 0000h~00ffh 128kb block754 02f2h 0000h~00ffh 128kb block723 02d3h 0000h~00ffh 128kb block755 02f3h 0000h~00ffh 128kb block724 02d4h 0000h~00ffh 128kb block756 02f4h 0000h~00ffh 128kb block725 02d5h 0000h~00ffh 128kb block757 02f5h 0000h~00ffh 128kb block726 02d6h 0000h~00ffh 128kb block758 02f6h 0000h~00ffh 128kb block727 02d7h 0000h~00ffh 128kb block759 02f7h 0000h~00ffh 128kb block728 02d8h 0000h~00ffh 128kb block760 02f8h 0000h~00ffh 128kb block729 02d9h 0000h~00ffh 128kb block761 02f9h 0000h~00ffh 128kb block730 02dah 0000h~00ffh 128kb block762 02fah 0000h~00ffh 128kb block731 02dbh 0000h~00ffh 128kb block763 02fbh 0000h~00ffh 128kb block732 02dch 0000h~00ffh 128kb block764 02fch 0000h~00ffh 128kb block733 02ddh 0000h~00ffh 128kb block765 02fdh 0000h~00ffh 128kb block734 02deh 0000h~00ffh 128kb block766 02feh 0000h~00ffh 128kb block735 02dfh 0000h~00ffh 128kb block767 02ffh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 27 - block block address page and sector address size block block address page and sector address size block768 0300h 0000h~00ffh 128kb block800 0320h 0000h~00ffh 128kb block769 0301h 0000h~00ffh 128kb block801 0321h 0000h~00ffh 128kb block770 0302h 0000h~00ffh 128kb block802 0322h 0000h~00ffh 128kb block771 0303h 0000h~00ffh 128kb block803 0323h 0000h~00ffh 128kb block772 0304h 0000h~00ffh 128kb block804 0324h 0000h~00ffh 128kb block773 0305h 0000h~00ffh 128kb block805 0325h 0000h~00ffh 128kb block774 0306h 0000h~00ffh 128kb block806 0326h 0000h~00ffh 128kb block775 0307h 0000h~00ffh 128kb block807 0327h 0000h~00ffh 128kb block776 0308h 0000h~00ffh 128kb block808 0328h 0000h~00ffh 128kb block777 0309h 0000h~00ffh 128kb block809 0329h 0000h~00ffh 128kb block778 030ah 0000h~00ffh 128kb block810 032ah 0000h~00ffh 128kb block779 030bh 0000h~00ffh 128kb block811 032bh 0000h~00ffh 128kb block780 030ch 0000h~00ffh 128kb block812 032ch 0000h~00ffh 128kb block781 030dh 0000h~00ffh 128kb block813 032dh 0000h~00ffh 128kb block782 030eh 0000h~00ffh 128kb block814 032eh 0000h~00ffh 128kb block783 030fh 0000h~00ffh 128kb block815 032fh 0000h~00ffh 128kb block784 0310h 0000h~00ffh 128kb block816 0330h 0000h~00ffh 128kb block785 0311h 0000h~00ffh 128kb block817 0331h 0000h~00ffh 128kb block786 0312h 0000h~00ffh 128kb block818 0332h 0000h~00ffh 128kb block787 0313h 0000h~00ffh 128kb block819 0333h 0000h~00ffh 128kb block788 0314h 0000h~00ffh 128kb block820 0334h 0000h~00ffh 128kb block789 0315h 0000h~00ffh 128kb block821 0335h 0000h~00ffh 128kb block790 0316h 0000h~00ffh 128kb block822 0336h 0000h~00ffh 128kb block791 0317h 0000h~00ffh 128kb block823 0337h 0000h~00ffh 128kb block792 0318h 0000h~00ffh 128kb block824 0338h 0000h~00ffh 128kb block793 0319h 0000h~00ffh 128kb block825 0339h 0000h~00ffh 128kb block794 031ah 0000h~00ffh 128kb block826 033ah 0000h~00ffh 128kb block795 031bh 0000h~00ffh 128kb block827 033bh 0000h~00ffh 128kb block796 031ch 0000h~00ffh 128kb block828 033ch 0000h~00ffh 128kb block797 031dh 0000h~00ffh 128kb block829 033dh 0000h~00ffh 128kb block798 031eh 0000h~00ffh 128kb block830 033eh 0000h~00ffh 128kb block799 031fh 0000h~00ffh 128kb block831 033fh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 28 - block block address page and sector address size block block address page and sector address size block832 0340h 0000h~00ffh 128kb block864 0360h 0000h~00ffh 128kb block833 0341h 0000h~00ffh 128kb block865 0361h 0000h~00ffh 128kb block834 0342h 0000h~00ffh 128kb block866 0362h 0000h~00ffh 128kb block835 0343h 0000h~00ffh 128kb block867 0363h 0000h~00ffh 128kb block836 0344h 0000h~00ffh 128kb block868 0364h 0000h~00ffh 128kb block837 0345h 0000h~00ffh 128kb block869 0365h 0000h~00ffh 128kb block838 0346h 0000h~00ffh 128kb block870 0366h 0000h~00ffh 128kb block839 0347h 0000h~00ffh 128kb block871 0367h 0000h~00ffh 128kb block840 0348h 0000h~00ffh 128kb block872 0368h 0000h~00ffh 128kb block841 0349h 0000h~00ffh 128kb block873 0369h 0000h~00ffh 128kb block842 034ah 0000h~00ffh 128kb block874 036ah 0000h~00ffh 128kb block843 034bh 0000h~00ffh 128kb block875 036bh 0000h~00ffh 128kb block844 034ch 0000h~00ffh 128kb block876 036ch 0000h~00ffh 128kb block845 034dh 0000h~00ffh 128kb block877 036dh 0000h~00ffh 128kb block846 034eh 0000h~00ffh 128kb block878 036eh 0000h~00ffh 128kb block847 034fh 0000h~00ffh 128kb block879 036fh 0000h~00ffh 128kb block848 0350h 0000h~00ffh 128kb block880 0370h 0000h~00ffh 128kb block849 0351h 0000h~00ffh 128kb block881 0371h 0000h~00ffh 128kb block850 0352h 0000h~00ffh 128kb block882 0372h 0000h~00ffh 128kb block851 0353h 0000h~00ffh 128kb block883 0373h 0000h~00ffh 128kb block852 0354h 0000h~00ffh 128kb block884 0374h 0000h~00ffh 128kb block853 0355h 0000h~00ffh 128kb block885 0375h 0000h~00ffh 128kb block854 0356h 0000h~00ffh 128kb block886 0376h 0000h~00ffh 128kb block855 0357h 0000h~00ffh 128kb block887 0377h 0000h~00ffh 128kb block856 0358h 0000h~00ffh 128kb block888 0378h 0000h~00ffh 128kb block857 0359h 0000h~00ffh 128kb block889 0379h 0000h~00ffh 128kb block858 035ah 0000h~00ffh 128kb block890 037ah 0000h~00ffh 128kb block859 035bh 0000h~00ffh 128kb block891 037bh 0000h~00ffh 128kb block860 035ch 0000h~00ffh 128kb block892 037ch 0000h~00ffh 128kb block861 035dh 0000h~00ffh 128kb block893 037dh 0000h~00ffh 128kb block862 035eh 0000h~00ffh 128kb block894 037eh 0000h~00ffh 128kb block863 035fh 0000h~00ffh 128kb block895 037fh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 29 - block block address page and sector address size block block address page and sector address size block896 0380h 0000h~00ffh 128kb block928 03a0h 0000h~00ffh 128kb block897 0381h 0000h~00ffh 128kb block929 03a1h 0000h~00ffh 128kb block898 0382h 0000h~00ffh 128kb block930 03a2h 0000h~00ffh 128kb block899 0383h 0000h~00ffh 128kb block931 03a3h 0000h~00ffh 128kb block900 0384h 0000h~00ffh 128kb block932 03a4h 0000h~00ffh 128kb block901 0385h 0000h~00ffh 128kb block933 03a5h 0000h~00ffh 128kb block902 0386h 0000h~00ffh 128kb block934 03a6h 0000h~00ffh 128kb block903 0387h 0000h~00ffh 128kb block935 03a7h 0000h~00ffh 128kb block904 0388h 0000h~00ffh 128kb block936 03a8h 0000h~00ffh 128kb block905 0389h 0000h~00ffh 128kb block937 03a9h 0000h~00ffh 128kb block906 038ah 0000h~00ffh 128kb block938 03aah 0000h~00ffh 128kb block907 038bh 0000h~00ffh 128kb block939 03abh 0000h~00ffh 128kb block908 038ch 0000h~00ffh 128kb block940 03ach 0000h~00ffh 128kb block909 038dh 0000h~00ffh 128kb block941 03adh 0000h~00ffh 128kb block910 038eh 0000h~00ffh 128kb block942 03aeh 0000h~00ffh 128kb block911 038fh 0000h~00ffh 128kb block943 03afh 0000h~00ffh 128kb block912 0390h 0000h~00ffh 128kb block944 03b0h 0000h~00ffh 128kb block913 0391h 0000h~00ffh 128kb block945 03b1h 0000h~00ffh 128kb block914 0392h 0000h~00ffh 128kb block946 03b2h 0000h~00ffh 128kb block915 0393h 0000h~00ffh 128kb block947 03b3h 0000h~00ffh 128kb block916 0394h 0000h~00ffh 128kb block948 03b4h 0000h~00ffh 128kb block917 0395h 0000h~00ffh 128kb block949 03b5h 0000h~00ffh 128kb block918 0396h 0000h~00ffh 128kb block950 03b6h 0000h~00ffh 128kb block919 0397h 0000h~00ffh 128kb block951 03b7h 0000h~00ffh 128kb block920 0398h 0000h~00ffh 128kb block952 03b8h 0000h~00ffh 128kb block921 0399h 0000h~00ffh 128kb block953 03b9h 0000h~00ffh 128kb block922 039ah 0000h~00ffh 128kb block954 03bah 0000h~00ffh 128kb block923 039bh 0000h~00ffh 128kb block955 03bbh 0000h~00ffh 128kb block924 039ch 0000h~00ffh 128kb block956 03bch 0000h~00ffh 128kb block925 039dh 0000h~00ffh 128kb block957 03bdh 0000h~00ffh 128kb block926 039eh 0000h~00ffh 128kb block958 03beh 0000h~00ffh 128kb block927 039fh 0000h~00ffh 128kb block959 03bfh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 30 - block block address page and sector address size block block address page and sector address size block960 03c0h 0000h~00ffh 128kb block992 03e0h 0000h~00ffh 128kb block961 03c1h 0000h~00ffh 128kb block993 03e1h 0000h~00ffh 128kb block962 03c2h 0000h~00ffh 128kb block994 03e2h 0000h~00ffh 128kb block963 03c3h 0000h~00ffh 128kb block995 03e3h 0000h~00ffh 128kb block964 03c4h 0000h~00ffh 128kb block996 03e4h 0000h~00ffh 128kb block965 03c5h 0000h~00ffh 128kb block997 03e5h 0000h~00ffh 128kb block966 03c6h 0000h~00ffh 128kb block998 03e6h 0000h~00ffh 128kb block967 03c7h 0000h~00ffh 128kb block999 03e7h 0000h~00ffh 128kb block968 03c8h 0000h~00ffh 128kb block1000 03e8h 0000h~00ffh 128kb block969 03c9h 0000h~00ffh 128kb block1001 03e9h 0000h~00ffh 128kb block970 03cah 0000h~00ffh 128kb block1002 03eah 0000h~00ffh 128kb block971 03cbh 0000h~00ffh 128kb block1003 03ebh 0000h~00ffh 128kb block972 03cch 0000h~00ffh 128kb block1004 03ech 0000h~00ffh 128kb block973 03cdh 0000h~00ffh 128kb block1005 03edh 0000h~00ffh 128kb block974 03ceh 0000h~00ffh 128kb block1006 03eeh 0000h~00ffh 128kb block975 03cfh 0000h~00ffh 128kb block1007 03efh 0000h~00ffh 128kb block976 03d0h 0000h~00ffh 128kb block1008 03f0h 0000h~00ffh 128kb block977 03d1h 0000h~00ffh 128kb block1009 03f1h 0000h~00ffh 128kb block978 03d2h 0000h~00ffh 128kb block1010 03f2h 0000h~00ffh 128kb block979 03d3h 0000h~00ffh 128kb block1011 03f3h 0000h~00ffh 128kb block980 03d4h 0000h~00ffh 128kb block1012 03f4h 0000h~00ffh 128kb block981 03d5h 0000h~00ffh 128kb block1013 03f5h 0000h~00ffh 128kb block982 03d6h 0000h~00ffh 128kb block1014 03f6h 0000h~00ffh 128kb block983 03d7h 0000h~00ffh 128kb block1015 03f7h 0000h~00ffh 128kb block984 03d8h 0000h~00ffh 128kb block1016 03f8h 0000h~00ffh 128kb block985 03d9h 0000h~00ffh 128kb block1017 03f9h 0000h~00ffh 128kb block986 03dah 0000h~00ffh 128kb block1018 03fah 0000h~00ffh 128kb block987 03dbh 0000h~00ffh 128kb block1019 03fbh 0000h~00ffh 128kb block988 03dch 0000h~00ffh 128kb block1020 03fch 0000h~00ffh 128kb block989 03ddh 0000h~00ffh 128kb block1021 03fdh 0000h~00ffh 128kb block990 03deh 0000h~00ffh 128kb block1022 03feh 0000h~00ffh 128kb block991 03dfh 0000h~00ffh 128kb block1023 03ffh 0000h~00ffh 128kb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 31 - 2.7.2 internal memory spare area assignment the figure below shows the assignment of the sp are area in the internal memory nand array. spare area assignment in the internal memory nand array information note 5 : for all blocks, 8th word is available to the user. however,in case of otp block, 8th word of sector 0, page 0 is reserved as otp locking bit area. therefore, in case of otp block, user usage on this area is prohibited. word byte note description 1 lsb 1 invalid block information in 1s t and 2nd page of an invalid block msb 2 lsb 2 managed by internal ecc logic for logical sector number data msb 3 lsb msb 3 reserved for future use 4 lsb msb 5 lsb dedicated to internal ecc logic. read only. eccm 1st for main area data msb dedicated to internal ecc logic. read only. eccm 2nd for main area data 6 lsb dedicated to internal ecc logic. read only. eccm 3rd for main area data msb dedicated to internal ecc logic. read only. eccs 1st for 2nd word of spare area data 7 lsb dedicated to internal ecc logic. read only. eccs 2nd for 3rd word of spare area data msb 3 reserved for future use 8 lsb 4 available to the user (note 5) msb main area 256w main area 256w main area 256w main area 256w spare area 8w spare area 8w spare area 8w spare area 8w { 1 st w eccm 1st eccm 2nd eccm 3rd eccs 1st eccs 2nd lsb msb lsb msb { 2 nd w lsb msb { 3 rd w lsb msb { 4 th w lsb msb { 5 th w lsb msb { 6 th w lsb msb { 7 th w lsb msb { 8 th w lsb msb note1 note1 note2 note2 note2 note3 note3 note3 note4 note4 note3
onenand1gb(KFG1G16Q2C-xebx) flash memory - 32 - 2.7.3 external memory (bufferram) address map the following table shows the external me mory address map in word and byte order. note that the data output is unknown while host reads a register bit of reserved area. division address (word order) address (byte order) size (total 128kb) usage description main area (64kb) 0000h~00ffh 00000h~001feh 512b 1kb r bootm 0 bootram main sector0 0100h~01ffh 00200h~003feh 512b bootm 1 bootram main sector1 0200h~02ffh 00400h~005feh 512b 4kb r/w datam 0_0 dataram main page0/sector0 0300h~03ffh 00600h~007feh 512b datam 0_1 dataram main page0/sector1 0400h~04ffh 00800h~009feh 512b datam 0_2 dataram main page0/sector2 0500h~05ffh 00a00h~00bfeh 512b datam 0_3 dataram main page0/sector3 0600h~06ffh 00c00h~00dfeh 512b datam 1_0 dataram main page1/sector0 0700h~07ffh 00e00h~00ffeh 512b datam 1_1 dataram main page1/sector1 0800h~08ffh 01000h~011feh 512b datam 1_2 dataram main page1/sector2 0900h~09ffh 01200h~013feh 512b datam 1_3 dataram main page1/sector3 0a00h~7fffh 01400h~0fffeh 59k 59k - reserved reserved spare area (8kb) 8000h~8007h 10000h~1000eh 16b 32b r boots 0 bootram spare sector0 8008h~800fh 10010h~1001eh 16b boots 1 bootram spare sector1 8010h~8017h 10020h~1002eh 16b 128b r/w datas 0_0 dataram spare page0/sector0 8018h~801fh 10030h~1003eh 16b datas 0_1 dataram spare page0/sector1 8020h~8027h 10040h~1004eh 16b datas 0_2 dataram spare page0/sector2 8028h~802fh 10050h~1005eh 16b datas 0_3 dataram spare page0/sector3 8030h~8037h 10060h~1006eh 16b datas 1_0 dataram spare page1/sector0 8038h~803fh 10070h~1007eh 16b datas 1_1 dataram spare page1/sector1 8040h~8047h 10080h~1008eh 16b datas 1_2 dataram spare page1/sector2 8048h~804fh 10090h~1009eh 16b datas 1_3 dataram spare page1/sector3 8050h~8fffh 100a0h~11ffeh 8032b 8032b - reserved reserved reserved (24kb) 9000h~bfffh 12000h~17ffeh 24kb 24kb - reserved reserved reserved (8kb) c000h~cfffh 18000h~19ffeh 8kb 8kb - reserved reserved reserved (16kb) d000h~efffh 1a000h~1dffeh 16kb 16kb - reserved reserved registers (8kb) f000h~ffffh 1e000h~1fffeh 8kb 8kb r or r/w registers registers
onenand1gb(KFG1G16Q2C-xebx) flash memory - 33 - 2.7.4 external memory map detail information the tables below show word order address map inform ation for the bootram and dataram main and spare areas. ? bootram(main area) -0000h~01ffh: 2(sector) x 512byte(nand main area) = 1kb ? dataram(main area) -0200h~09ffh: 8(sector) x 512byte(nand main area) = 4kb ? bootram(spare area) -8000h~800fh: 2(sector) x 16byte(nand spare area) = 32b ? dataram(spare area) -8010h~804fh: 8(sector) x 16byte(nand spare area) = 128b *nand flash array consists of 2kb page size and 128kb block size. 0000h~00ffh(512b) bootm 0 (sector 0 of page 0) 0100h~01ffh(512b) bootm 1 (sector 1 of page 0) 0200h~02ffh(512b) datam 0_0 (sector 0 of page 0) 0300h~03ffh(512b) datam 0_1 (sector 1 of page 0) 0400h~04ffh(512b) datam 0_2 (sector 2 of page 0) 0500h~05ffh(512b) datam 0_3 (sector 3 of page 0) 0600h~06ffh(512b) datam 1_0 (sector 0 of page 1) 0700h~07ffh(512b) datam 1_1 (sector 1 of page 1) 0800h~08ffh(512b) datam 1_2 (sector 2 of page 1) 0900h~09ffh(512b) datam 1_3 (sector 3 of page 1) 8000h~8007h(16b) boots 0 (sector 0 of page 0) 8008h~800fh(16b) boots 1 (sector 1 of page 0) 8010h~8017h(16b) datas 0_0 (sector 0 of page 0) 8018h~801fh(16b) datas 0_1 (sector 1 of page 0) 8020h~8027h(16b) datas 0_2 (sector 2 of page 0) 8028h~802fh(16b) datas 0_3 (sector 3 of page 0) 8030h~8037h(16b) datas 1_0 (sector 0 of page 1) 8038h~803fh(16b) datas 1_1 (sector 1 of page 1) 8040h~8047h(16b) datas 1_2 (sector 2 of page 1) 8048h~804fh(16b) datas 1_3 (sector 3 of page 1)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 34 - 2.7.5 external memory spare area assignment buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 boots 0 8000h 10000h bi 8001h 10002h managed by internal ecc logic 8002h 10004h reserved for the future use managed by internal ecc logic 8003h 10006h reserved for the current and future use 8004h 10008h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8005h 1000ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8006h 1000ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8007h 1000eh free usage boots 1 8008h 10010h bi 8009h 10012h managed by internal ecc logic 800ah 10014h reserved for the future use managed by internal ecc logic 800bh 10016h reserved for the current and future use 800ch 10018h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 800dh 1001ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 800eh 1001ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 800fh 1001eh free usage datas 0_0 8010h 10020h bi 8011h 10022h managed by internal ecc logic 8012h 10024h reserved for the future use managed by internal ecc logic 8013h 10026h reserved for the current and future use 8014h 10028h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8015h 1002ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8016h 1002ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8017h 1002eh free usage datas 0_1 8018h 10030h bi 8019h 10032h managed by internal ecc logic 801ah 10034h reserved for the future use managed by internal ecc logic 801bh 10036h reserved for the current and future use 801ch 10038h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 801dh 1003ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 801eh 1003ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 801fh 1003eh free usage equivalent to 1word of nand flash
onenand1gb(KFG1G16Q2C-xebx) flash memory - 35 - buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 datas 0_2 8020h 10040h bi 8021h 10042h managed by internal ecc logic 8022h 10044h reserved for the future use managed by internal ecc logic 8023h 10046h reserved for the current and future use 8024h 10048h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8025h 1004ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8026h 1004ch reserved for the future use ecc code for spare area data (2 nd ) 8027h 1004eh free usage datas 0_3 8028h 10050h bi 8029h 10052h managed by internal ecc logic 802ah 10054h reserved for the future use managed by internal ecc logic 802bh 10056h reserved for the current and future use 802ch 10058h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 802dh 1005ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 802eh 1005ch reserved for the future use ecc code for spare area data (2 nd ) 802fh 1005eh free usage datas 1_0 8030h 10060h bi 8031h 10062h managed by internal ecc logic 8032h 10064h reserved for the future use managed by internal ecc logic 8033h 10066h reserved for the current and future use 8034h 10068h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8035h 1006ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8036h 1006ch reserved for the future use ecc code for spare area data (2 nd ) 8037h 1006eh free usage datas 1_1 8038h 10070h bi 8039h 10072h managed by internal ecc logic 803ah 10074h reserved for the future use managed by internal ecc logic 803bh 10076h reserved for the current and future use 803ch 10078h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 803dh 1007ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 803eh 1007ch reserved for the future use ecc code for spare area data (2 nd ) 803fh 1007eh free usage datas 1_2 8040h 10080h bi 8041h 10082h managed by internal ecc logic 8042h 10084h reserved for the future use managed by internal ecc logic 8043h 10086h reserved for the current and future use 8044h 10088h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8045h 1008ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8046h 1008ch reserved for the future use ecc code for spare area data (2 nd ) 8047h 1008eh free usage
onenand1gb(KFG1G16Q2C-xebx) flash memory - 36 - note : - bi: bad block information >host can use complete spare area except bi and ecc code area. for example, host can write data to spare area buffer except for the area controlled by ecc logic at program operation. >in case of ?with ecc? mode, onenand automatically generates ecc code for both main and spare data of memory during program ope ration, but does not update ecc code to spare bufferram during load operation. >when loading/programming spare area, spare area bufferram address( bsa) and bufferram sector count (bsc) is chosen via start bu ffer register as it is. buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 datas 1_3 8048h 10090h bi 8049h 10092h managed by internal ecc logic 804ah 10094h reserved for the future use managed by internal ecc logic 804bh 10096h reserved for the current and future use 804ch 10098h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 804dh 1009ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 804eh 1009ch reserved for the future use ecc code for spare area data (2 nd ) 804fh 1009eh free usage equivalent to 1word of nand flash equivalent to 1word of nand flash
onenand1gb(KFG1G16Q2C-xebx) flash memory - 37 - 2.8 registers section 2.8 of this specification provides information about the onenand registers. 2.8.1 register address map this map describes the register addresses, register name, register description, and host accessibility. address (word order) address (byte order) name host access description f000h 1e000h manufacturer id r manufacturer identification f001h 1e002h device id r device identification f002h 1e004h version id r n/a f003h 1e006h data buffer size r data buffer size f004h 1e008h boot buffer size r boot buffer size f005h 1e00ah amount of buffers r amount of data/boot buffers f006h 1e00ch technology r info about technology f007h~f0ffh 1e00eh~1e1feh re served - reserved for user f100h 1e200h start address 1 r/w nand flash block address f101h 1e202h start address 2 - n/a f102h 1e204h start address 3 r/w destination block address for copy back program f103h 1e206h start address 4 r/w destination page & sector address for copy back program f104h 1e208h start address 5 r/w number of page in synchronous burst block read f105h 1e20ah start address 6 - n/a f106h 1e20ch start address 7 - n/a f107h 1e20eh start address 8 r/w nand flash page & sector address f108h~f1ffh 1e210h~1e3feh reserved - reserved for user f200h 1e400h start buffer r/w buffer number for the page data transfer to/from the mem- ory and the start buffer address the meaning is with which buffer to start and how many buffers to use for the data transfer f201h~f207h 1e402h~1e40eh reserved - reserved for user f208h~f21fh 1e410h~1e43eh reserved - rese rved for vendor specific purposes f220h 1e440h command r/w host control and memory operation commands f221h 1e442h system configuration 1 r, r/w memory and host interface configuration f222h 1e444h system configuration 2 -n/a f223h~f22fh 1e446h~1e45eh reserved - reserved for user f230h~f23fh 1e460h~1e47eh reserved - rese rved for vendor specific purposes f240h 1e480h controller status r controller status and result of memory operation f241h 1e482h interrupt r/w memory command completion interrupt status f242h~f24bh 1e484h~1e496h reserved - reserved for user f24ch 1e498h start block address r/w start memory block address in write protection mode
onenand1gb(KFG1G16Q2C-xebx) flash memory - 38 - 2.8.2 manufacturer id register f000h (r) this read register describes t he manufacturer's identification. samsung electronics company manufacturer's id is 00ech. f000h, default = 00ech address (word order) address (byte order) name host access description f24dh 1e49ah reserved - reserved for user f24eh 1e49ch write protection status r current memory write protection status (unlocked/locked/tight-locked) f24fh~feffh 1e49eh~1fdfeh reserved - reserved for user ff00h 1fe00h ecc status register r ecc status of sector ff01h 1fe02h ecc result of main area data r ecc error position of main area data error for first selected sector ff02h 1fe04h ecc result of spare area data r ecc error position of spare area data error for first selected sector ff03h 1fe06h ecc result of main area data r ecc error position of main area data error for second selected sector ff04h 1fe08h ecc result of spare area data r ecc error position of spare area data error for second selected sector ff05h 1fe0ah ecc result of main area data r ecc error position of main area data error for third selected sector ff06h 1fe0ch ecc result of spare area data r ecc error position of spare area data error for third selected sector ff07h 1fe0eh ecc result of main area data r ecc error position of main area data error for fourth selected sector ff08h 1fe10h ecc result of spare area data r ecc error position of spare area data error for fourth selected sector ff09h~ffffh 1fe12h~1fffeh reserved - reserved for vendor specific purposes 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 manufid
onenand1gb(KFG1G16Q2C-xebx) flash memory - 39 - 2.8.3 device id register f001h (r) this read register describes the device. f001h, see table for default. device identification device id default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 deviceid register information description deviceid [1:0] vcc 00 = 1.8v, 01/10/11 = reserved deviceid [2] muxed/demuxed 0 = muxed, 1 = demuxed deviceid [3] single/ddp 0 = single, 1 = ddp deviceid [7:4] density 0000 = 128mb, 0001 = 256mb, 0010 = 512mb, 0011 = 1gb, 0100 = 2gb, 0101=4gb deviceid [8] bottom boot 0 = bottom boot device deviceid[15:0] KFG1G16Q2C 0034h
onenand1gb(KFG1G16Q2C-xebx) flash memory - 40 - 2.8.4 version id register f002h this register is reserved for internal use. 2.8.5 data buffer size register f003h (r) this read register describes the size of the data buffer. f003h, default = 0800h data buffer size information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 databufsize register information description databufsize total data buffer size in words equal to 2 buffers of 1024 words each (2 x 1024 = 2 11 ) in the memory interface
onenand1gb(KFG1G16Q2C-xebx) flash memory - 41 - 2.8.6 boot buffer size register f004h (r) this read register describes the size of the boot buffer. f004h, default = 0200h 2.8.7 number of buffers register f005h (r) this read register describes the number of each buffer. f005h, default = 0201h number of buffers information 2.8.8 technology register f006h (r) this read register describes the internal nand array technology. f006h, default = 0000h technology information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bootbufsize register information description bootbufsize total boot buffer size in words equal to 1 buffer of 512 words (1 x 512 = 2 9 ) in the memory interface 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 databufamount bootbufamount register information description databufamount the number of data buffers = 2 (2 n , n=1) bootbufamount the number of boot buffers = 1 (2 n , n=0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 te c h technology register setting nand slc 0000h nand mlc 0001h reserved 0002h ~ ffffh
onenand1gb(KFG1G16Q2C-xebx) flash memory - 42 - 2.8.9 start address1 register f100h (r/w) this read/write register describes the nand flash block address which will be loaded, programmed, or erased. f100h, default = 0000h start address1 information 2.8.10 start address2 register f101h (r/w) this register is reserved for future use. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(000000) fba device number of block fba 1gb 1024 fba[9:0] register information description fba nand flash block address
onenand1gb(KFG1G16Q2C-xebx) flash memory - 43 - 2.8.11 start address3 register f102h (r/w) this read/write register describes the na nd flash destination block address which will be copy back programmed. also, this regi ster indi- cates the block address for the first page to be read in cache read operation. f102h, default = 0000h start address3 information 2.8.12 start address4 register f103h (r/w) this read/write register describes the nand flash destination page address in a blo ck and the nand flash destination sector add ress in a page for copy back programming. also, this register describes the first page and sector address to be loaded in cache read oper ation. f103h, default = 0000h note : 1) in case of ?cache read operation?, fcsa has to be set to 00. start address4 information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(000000) fcba device number of block fba 1gb 1024 fcba[9:0] register information description fcba nand flash copy back block address & block address for the first page to be read in cache read operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) fcpa fcsa 1) item description default value range fcpa nand flash copy back page address & first page address of cache read 000000 000000 ~ 111111, 6 bits for 64 pages fcsa nand flash copy back sector address & first sector address of cache read 00 00 ~ 11, 2 bits for 4 sectors
onenand1gb(KFG1G16Q2C-xebx) flash memory - 44 - 2.8.13 start address5 register f104h (r/w) this read/write register describes the num ber of page in synchronous burst block read. f104h, default = 0000h flash page count (fpc) information note : synchronous burst block read are not abl e to be perforformed with 1 or 2pages. 2.8.14 start address6 register f105h this register is reserved for future use. 2.8.15 start address7 register f106h this register is reserved for future use. 2.8.16 start address8 register f107h (r/w) this read/write register describes the nand flash start page addr ess in a block for a page load, copy back program, or program operation and the nand flash start sector address in a page fo r a load, copy back program, or program operation. f107h, default = 0000h note : 1) in case of ? synchronous burst block read?, ?cache read operation?, fsa has to be set to 00. start address8 information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) fpc fpc number of page 000000 (default) 64 page 000011 3 page 000100 4 page .. .. 111111 63 page 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved (00000000) fpa fsa 1) item description default value range fpa nand flash page address 000000 000000 ~ 111111, 6 bits for 64 pages fsa nand flash sector address 00 00 ~ 11, 2 bits for 4 sectors
onenand1gb(KFG1G16Q2C-xebx) flash memory - 45 - 2.8.17 start buffer register f200h (r/w) this read/write register describes the bufferram sect or count (bsc) and bufferram sector address (bsa). the bufferram sector count (bsc) field specifies the number of se ctors to be loaded, programmed, or copy back programmed. at 00 value (the default value), the number of sector is "4". if the internal ram buffer reaches its maximum value of 11, it will count up to 0 value to meet the bsc value. for example, if bsa = 1101, bsc = 00, then the selected bufferram will count up from '1101 1110 1111 1100'. the bufferram sector address (bsa) is the sector 0~3 address in the internal bootram and dataram where data is placed. f200h, default = 0000h note : in case of ?cache read?, bsa has to be set to 1000, and bsc has to be set to 00. in case of ?synchronous burst block read?, bsa has to be set to 1000 or 1100, and bsc has to be set to 00. start address8 information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) bsa reserved(000000) bsc item description bsa[3] selection bit between bootram and dataram bsa[2] selection bit between dataram0 and dataram1 bsa[1:0] selection bit between sector0 and sector1 in the internal bootram selection bit between sector0 to sector3 in the internal dataram bsc number of sectors 01 1 sector 10 2 sector 11 3 sector 00 4 sector bootram 0 bootram 1 bootram sector: (512 + 16) byte dataram 1_0 dataram 1_1 dataram 1_2 dataram 1_3 dataram1 0000 0001 1100 1101 1110 1111 { main area data { spare area data bsa dataram 0_0 dataram 0_1 dataram 0_2 dataram 0_3 dataram0 1000 1001 1010 1011 512b 16b
onenand1gb(KFG1G16Q2C-xebx) flash memory - 46 - 2.8.18 command register f220h (r/w) command can be issued by two following methods, and user ma y select one way or the other to issue appropriate command; 1. write command into command register when int is at ready state. int will automatically turn to busy state as command is issu ed. once the desired operation is completed, int will go back ready state. 2. write 0000h to int bit of interrupt status register, and then write command into command register. once the desired operatio n is com- pleted, int will go back to ready state. (00f0h and 00f3h may be accepted during busy state of some operati ons. refer to the rightmost column of the command register ta ble below.) f220h, default = 0000h note : 1) 0080h programs both main and spare area, while 001ah programs only spare area. refer to chapter 5.9 for nop limits in issuin g these commands. when using 0080h and 001ah command, read-only part in spare area must be masked by ff. (refer to chapter 2.7.2) 2) if any blocks are changed to locked-tight state, the all block unlock command will fail. in order to use all block unlock co mmand again, a cold reset is needed. 3) ?reset onenand?(=hot reset) command makes the registers and nand flash core into default state. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command cmd operation acceptable command during busy 0000h load single/multiple sector data unit into buffer 00f0h, 00f3h 0013h load single/multiple spare sector into buffer 00f0h, 00f3h 0080h program single/multiple sector data unit from buffer 1) 00f0h, 00f3h 001ah program single/multiple spare data unit from buffer 00f0h, 00f3h 001bh copy back program operation 00f0h, 00f3h 0023h unlock nand array a block 00f0h, 00f3h 002ah lock nand array a block 00f0h, 00f3h 002ch lock-tight nand array a block 00f0h, 00f3h 0027h all block unlock 2) 00f0h, 00f3h 0071h erase verify read 00f0h, 00f3h 000eh cache read 00f0h, 00f3h 000ch finish cache read 00f0h, 00f3h 000ah synchronous burst block read 00f0h, 00f3h 0094h block erase 00f0h, 00f3h 0095h multi-block erase 00f0h, 00f3h 00b0h erase suspend 00f0h, 00f3h 0030h erase resume 00f0h, 00f3h 00f0h reset nand flash core - 00f3h reset onenand 3) - 0065h otp access 00f0h, 00f3h
onenand1gb(KFG1G16Q2C-xebx) flash memory - 47 - 2.8.18.1 two methods to clear interrupt register in command input to clear interrupt register in command input, us er may select one from either following methods. first method is to turn int to low by manually writing 0000h to int bit of interrupt register. 1) second method is input command while int is high, and the device will automatic ally turn int to low. 1) (second method is equivalent with method used in general nand flash) user may choose the desirable method to clear interrupt register. method 1: manually set int=0 before writing command into command register: manual int mode (1) clear interrupt register (f241h) by writing 0000h into int bi t of interrupt register. this operation will make int pin turn low. 1) (2) write command into command register. this will make the device to perform the designated operation. (3) int pin will turn back to high once the operation is completed. 1) note 1) int pin polarity is based on ?iobe=1 and int pol=1 (default)? setting method 2: write command into command register at int ready state: auto int mode (1) write command into command register. this wi ll automatically turn int from high to low. 1) (2) int pin will turn back to high once the operation is completed. 1) note 1) int pin polarity is based on ?iobe=1 and int pol=1 (default)? setting write 0 into int bit of interrupt register write command into command register int will automatically turn to high when designated operation is completed. int pin 1) int bit write command into command register int will automatically turn to busy state int will automatically turn back to ready state when designated operation in completed. int pin 1) int bit
onenand1gb(KFG1G16Q2C-xebx) flash memory - 48 - 2.8.19 system configuration 1 register f221h (r, r/w) this read/write register descri bes the system configuration. f221h, default =40c0h read mode (rm) read mode information[15] burst read write latency (brwl) * default value of brwl and hf value is brwl=4, hf=0. for host frequency over 66mhz, brwl should be 6 or 7 while hf is 1. for host frequency range of 40mhz~66mhz, br wl should be set to 4~7 while hf is 0. for host frequency under 40mhz, brwl s hould be set to 3~7 while hf is 0. burst read write latency (brwl) information[14:12] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r rm brwl bl ecc rdy pol int pol iobe rdy conf reserv ed hf wm bwps rm read mode 0 asynchronous read(default) 1 synchronous read item definition description rm read mode selects between asynchronous read mode and synchronous read mode brwl latency cycles (read/write) under 40mhz (hf=0) 40mhz~66mhz (hf=0) over 66mhz (hf=1) 000~010 reserved 011 3(up to 40mhz. min) 3(n/a) 3(n/a) 100 (default) 4 4(min.) 4(n/a) 101 5 5 5(n/a) 110 6 6 6(min.) 111 777 item definition description brwl burst read latency / burst write latency specifies the access latency in the burst read / write transfer for the initial access
onenand1gb(KFG1G16Q2C-xebx) flash memory - 49 - burst length (bl) hosts must follow burst length set by bl when reading data in synchronous burst read. note : 1) for normal synchronous burst read, setting bl=000 (continuous) will read 1k words depending on the number of clocks. in usin g synchronous burst block read, setting bl=000 (continuous) will read the amount of data in a block set by number of page register. 2) even in using synchronous burst block read, it is possible to use above burst lengt h by setting bl register by following the above table. burst length (bl) information[11:9] error correction code (ecc) information[8] rdy polarity (rdypol) information[7] int polarity (intpol) information[6] bl burst length(main) burst length(spare) 000 continuous(default) 001 4 words 010 8 words 011 16 words 100 32 words n/a 101 1k words (block read only) n/a 110~111 reserved item definition description bl burst length specifies the size of the burst length during a synchronous linear burst read and wrap around. and also burst length during a synchronous linear burst write item definition description ecc error correction code operation 0 = with correction (default) 1 = without correction (bypassed) item definition description rdypol rdy signal polarity 1 = high for ready (default) 0 = low for ready intpol int bit of interrupt status register int pin output 0 0 (busy) high 1 (ready) low 1 (default) 0 (busy) low 1 (ready) high
onenand1gb(KFG1G16Q2C-xebx) flash memory - 50 - i/o buffer enable (iobe) iobe is the i/o buffer enable for the int and rdy signals. at startup, int and rdy outputs are high-z. bits 6 and 7 become vali d after iobe is set to "1". iobe can be reset by a cold reset or by writing "0" to bit 5 of system configuration1 register. i/o buffer enable information[5] rdy configuration (rdy conf) rdy configuration information[4] hf enable (hf) hf information[2] item definition description iobe i/o buffer enable for int and rdy signals 0 = disable (default) 1 = enable item definition description rdy conf rdy configuration 0=active one clock before valid data(default) 1=active with valid data hf description 0 hf disable (default, 66mhz and under) 1 hf enable (over 66mhz) item definition description hf high frequency selects between hf disable and hf enable
onenand1gb(KFG1G16Q2C-xebx) flash memory - 51 - write mode (wm) write mode information[1] mrs(mode register setting) description note : 1) operation not guaranteed for cases not defined in above table. boot buffer write protect status(bwps) boot buffer write protect status information[0] wm write mode 0 asynchronous write(default) 1 synchronous write item definition description wm write mode selects between asynchronous write mode and synchronouswrite mode rm wm mode description 0 0 asynch read & asynch write (default) 1 0 sync read & asynch write 1 1 sync read & synch write other case reserved 1) item definition description bwps boot buffer write protect status 0=locked(fixed)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 52 - 2.8.20 system configuration 2 register f222h this register is reserved for future use. 2.8.21 controller status register f240h (r) this read register shows the overall internal status of the onenand and the controller. f240h, default = 0000h ongo this bit shows the overall inter nal status of the onenand device. ongo information[15] lock this bit shows whether the host is loading data from the nand fl ash array into the locked bootram or whether the host is perfor ming a pro- gram/erase of a locked block of the nand flash array. lock information[14] load this bit shows the load operation status. load information[13] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ongo lock load prog erase error sus reserved (0) rstb otp l otp bl reserved(0000) to (0) item definition description ongo internal device status 0 = ready 1 = busy lock locked/unlocked check result 0unlocked 1locked item definition description load load operation status 0 = ready (default) 1 = busy or error (see controller status output modes)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 53 - program this bit shows the program operation status. program information[12] erase this bit shows the erase operation status. erase information[11] error this bit shows the overall error status, including load reset, program reset, and erase reset status. error information[10] erase suspend (sus) this bit shows the erase suspend status. sus information[9] item definition description prog program operation status 0 = ready (default) 1 = busy or error (see controller status output modes) item definition description erase erase operation status 0 = ready (default) 1 = busy or error (see controller status output modes) error sector/page load/program/copyback program and invalid command input 0pass 1fail sus erase suspend status 0 erase resume(default) 1 erase suspend, program ongoi ng(susp.), load ongoing(susp.), program fail(susp.), load fail(s usp.), invalid command(susp.)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 54 - reset / busy (rstb) this bit shows the reset operation status. rstb information[7] otp lock status (otp l ) this bit shows whether the otp block is locked or unlocked. locki ng the otp has the effect of a 'write-protect' to guard agains t accidental re- programming of data stored in the otp block. the otp l status bit is automatically updated at power-on. otp lock information[6] 1st block otp lock status (otp bl ) this bit shows whether the 1st bl ock otp is locked or unlocked. locking the 1st block otp has the effect of a 'program/erase pr otect' to guard against accidental re-programming of data stored in the 1st block. the otp bl status bit is automat ically updated at power-on. otp lock information[5] time out (to) this bit determines if there is a time out for load, program, copy back program, and erase operati ons. it is fixed at 'no time out'. to information[0] item definition description rstb reset operation status 0 = ready (default) 1 = busy (see controller status output modes) otp l otp locked/unlocked status 0 otp block unlock status(default) 1 otp block lock status(disable otp program/erase) otp bl 1st block otp locked/unlocked status 0 1st block otp unlock status(default) 1 1st block otplock status(disabl e 1st block otp program/erase) item definition description to time out 0 = no time out
onenand1gb(KFG1G16Q2C-xebx) flash memory - 55 - controller status register output modes note : 1) erm and/or ers bits in ecc status register at load fail case is 10. (2bits error - uncorrectable) if 2 bit error occurs during synchronous burs t block read operation, load fail mode will be shown. 2) erm and ers bits in ecc status register at load reset case are 00. (no error) 3) multi block erase status should be checked by erase verify read operation. 4) "1" for otp block lock, "0" for otp block unlock. 5) "1" for 1st block otp lock, "0" for 1st block otp unlock. 6) during cache read operation, load/cache read ongoing mode will be shown at the int high after ?cache read? command. load/cache read ok mode will be shown only at the completion of ?finish cache read? command. mode controller status register [15:0] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4:1] [0] ongo lock load prog erase error sus reserved (0) rstb otp l (note4) otp bl (note5) reserved (0) to load / cache read ongoing 6) 1 0 1 0 0 0 0 0 0 0/1 0/1 0000 0 program ongoing 1 0 0 1 0 0 0 0 0 0/1 0/1 0000 0 erase ongoing 1 0 0 0 1 0 0 0 0 0/1 0/1 0000 0 reset ongoing 1 0 0 0 0 0 0 0 1 0/1 0/1 0000 0 multi-block erase ongoing 1 0 0 0 1 0 0 0 0 0/1 0/1 0000 0 erase verify read ongoing 1 0 0 0 0 0 0 0 0 0/1 0/1 0000 0 load / cache read ok 6) 0 0 0 0 0 0 0 0 0 0/1 0/1 0000 0 program ok 0 0 0 0 0 0 0 0 0 0/1 0/1 0000 0 erase ok 0 0 0 0 0 0 0 0 0 0/1 0/1 0000 0 erase verify read ok 3) 0 0 0 0 0 0 0 0 0 0/1 0/1 0000 0 load fail 1) 0 0 1 0 0 1 0 0 0 0/1 0/1 0000 0 program fail 0 0 0 1 0 1 0 0 0 0/1 0/1 0000 0 erase fail 0 0 0 0 1 1 0 0 0 0/1 0/1 0000 0 cache read fail 1 0 1 0 0 1 0 0 0 0/1 0/1 0000 0 erase verify read fail 3) 0 0 0 0 1 1 0 0 0 0/1 0/1 0000 0 load reset 2) 0 0 1 0 0 1 0 0 1 0/1 0/1 0000 0 program reset 0 0 0 1 0 1 0 0 1 0/1 0/1 0000 0 erase reset 0 0 0 0 1 1 0 0 1 0/1 0/1 0000 0 erase suspend 0 0 0 0 1 0 1 0 0 0/1 0/1 0000 0 program lock 0 1 0 1 0 1 0 0 0 0/1 0/1 0000 0 erase lock 0 1 0 0 1 1 0 0 0 0/1 0/1 0000 0 load lock(buffer lock) 0 1 1 0 0 1 0 0 0 0/1 0/1 0000 0 otp program fail(lock) 0 1 0 1 0 1 0 0 0 1 1 0000 0 otp program fail 0 0 0 1 0 1 0 0 0 0 0 0000 0 otp erase fail 0 1 0 0 1 1 0 0 0 0/1 0/1 0000 0 program ongoing(susp.) 1 0 0 1 1 0 1 0 0 0/1 0/1 0000 0 load ongoing(susp.) 1 0 1 0 1 0 1 0 0 0/1 0/1 0000 0 program fail(susp.) 0 0 0 1 1 1 1 0 0 0/1 0/1 0000 0 load fail(susp.) 0 0 1 0 1 1 1 0 0 0/1 0/1 0000 0 invalid command 0 0 0 0 0 1 0 0 0 0/1 0/1 0000 0 invalid command(susp.) 0 0 0 0 1 1 1 0 0 0/1 0/1 0000 0
onenand1gb(KFG1G16Q2C-xebx) flash memory - 56 - 2.8.22 interrupt status register f241h (r/w) this read/write register shows status of the onenand interrupts. f241h, defaults = 8080h after cold reset; 8010h after warm/hot reset interrupt (int) this is the master interrupt bit. the int bit is wired directly to the int pin on the chip. upon writing '0' to the int bit, th e int pin goes low if intpol is high and goes high if intpol is low. int interrupt [15] read interrupt (ri) this is the read interrupt bit. ri interrupt [7] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 int reserved(0000000) ri wi ei rsti reserved(0000) status conditions default state valid state interrupt function cold warm/hot 11 0 off sets itself to ?1? one or more of ri, wi, rsti and ei is set to ?1?, or 0065h, 0023h, 0071h, 002ah, 0027h and 002ch commands are completed. 0 1 pending clears to ?0? ?0? is written to this bit, cold/warm/hot reset is being performed, or command is written to command register in int auto mode 1 0 off status conditions default state valid state interrupt function cold warm/hot 10 0 off sets itself to ?1? at the completion of an load operation (0000h, 000eh, 000ch, 000ah, 0013h, load data into buffer, or boot is done) 0 1 pending clears to ?0? ?0? is written to this bit, cold/warm/hot reset is being performed, or command is written to command register in int auto mode 1 0 off
onenand1gb(KFG1G16Q2C-xebx) flash memory - 57 - write interrupt (wi) this is the write interrupt bit. wi interrupt [6] erase interrupt (ei) this is the erase interrupt bit. ei interrupt [5] reset interrupt (rsti) this is the reset interrupt bit. rsti interrupt [4] status conditions default state valid state interrupt function cold warm/hot 00 0 off sets itself to ?1? at the completion of an program operation (0080h, 001ah, 001bh) 0 1 pending clears to ?0? ?0? is written to this bit, cold/warm/hot reset is being performed, or com- mand is written to command register in int auto mode 1 0 off status conditions default state valid state interrupt function cold warm/hot 00 0 off sets itself to ?1? at the completion of an erase operation (0094h, 0095h, 0030h) 0 1 pending clears to ?0? ?0? is written to this bit, cold/warm/hot reset is being performed, or com- mand is written to command register in int auto mode 1 0 off status conditions default state valid state interrupt function cold warm/hot 01 0 off sets itself to ?1? at the completion of an reset operation (00b0h, 00f0h, 00f3h or warm reset is released) 0 1 pending clears to ?0? ?0? is written to this bit, or command is written to command register in int auto mode 1 0 off
onenand1gb(KFG1G16Q2C-xebx) flash memory - 58 - 2.8.23 start block address register f24ch (r/w) this read/write register shows the nand fl ash block address in the write protection m ode. setting this register precedes a 'loc k block' command, 'unlock block' command, or ?lock-tight' command. f24ch, default = 0000h sba information[9:0] 2.8.24 end block address register f24dh this register is reserved for future use. 2.8.25 nand flash write protection status register f24eh (r) this read register shows the write protecti on status of the nand flash memory array. to read the write protection status, fba has to be set before reading the register . f24eh, default = 0002h write protection status information[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(000000) sba device number of block sba 1gb 1024 [9:0] item definition description sba start block address precedes lock block, unlock block, or lock-tight commands 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000000) us ls lts item definition description us unlocked status 1 = current nand flash block is unlocked ls locked status 1 = current nand flash block is locked or first block of nand flash array is locked to be otp lts locked-tight status 1 = current nand flash block is locked-tight
onenand1gb(KFG1G16Q2C-xebx) flash memory - 59 - 2.8.26 ecc status register ff00h (r) this read register shows the error correcti on status. the onenand can detect 1- or 2- bit errors and correct 1-bit errors. 3-bit or more error detection and correction is not supported. ecc can be performed on the nand flash main and spare memory areas . the ecc status register can also show the number of errors in a sector as a result of an ecc check in during a load operati on. ecc status bits are also updated during a boot loading operation . ecc registers will be reset when another command is issued. ff00h, default = 0000h note : 1) after synchronous block burst read operat ion, dq[0] shows accmulated 1bit error. error status ecc information[15:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 erm3 ers3 erm2 ers2 erm1 ers1 erm0 ers0 1) erm, ers ecc status 00 no error 01 1 bit error(correctable) 10 2 bit error (uncorrectable) 11 reserved item definition description erm0 1st selected sector of the main bufferram status of errors in the 1st selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. erm1 2nd selected sector of the main bufferram status of errors in the 2nd selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. erm2 3rd selected sector of the main bufferram status of errors in the 3rd selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. erm3 4th selected sector of the main bufferram status of errors in the 4th selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers0 1st selected sector of the spare bufferram status of errors in the 1st selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers1 2nd selected sector of the spare bufferram status of errors in the 2nd selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers2 3rd selected sector of the spare bufferram status of errors in the 3rd selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers3 4th selected sector of the spare bufferram status of errors in the 4th selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 60 - 2.8.27 ecc result of 1 st selected sector, main area data register ff01h (r) this read register shows the error correction result for the 1st selected sector of the main area data. eccposword0 is the erro r position address in the main area data of 256 words. eccposio0 is the error position address which selects 1 of 16 dqs. eccposword0 and eccposio0 are also updated at boot loading. ff01h, default = 0000h 2.8.28 ecc result of 1 st selected sector, spare area data register ff02h (r) this read register shows the error correction result for the 1st selected sector of the spare area data. ecclogsector0 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. ec cposio0 is the error position address which selects 1 of 16 dq s. ecclogsector0 and eccposio0 are also updated at boot loading. ff02h, default = 0000h 2.8.29 ecc result of 2 nd selected sector, main area data register ff03h (r) this read register shows the error correction result for the 2nd selected sector of the main area data. eccposword1 is the erro r position address in the main area data of 256 words. eccposio1 is the error position address which selects 1 of 16 dqs. eccposword1 and eccposio1 are also updated at boot loading. ff03h, default = 0000h 2.8.30 ecc result of 2 nd selected sector, spare area data register ff04h (r) this read register shows the error correction result for the 2nd selected sector of the spare area data. ecclogsector1 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. ec cposio1 is the error position address which selects 1 of 16 dq s. ecclogsector1 and eccposio1 are also updated at boot loading. ff04h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword0 eccposio0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector0 eccposio0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword1 eccposio1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector1 eccposio1
onenand1gb(KFG1G16Q2C-xebx) flash memory - 61 - 2.8.31 ecc result of 3 rd selected sector, main area data register ff05h (r) this read register shows the error correction result for the 3rd selected sector of the main area data. eccposword2 is the erro r position address in the main area data of 256 words. eccposio2 is the error position address which selects 1 of 16 dqs. eccposword2 and eccposio2 are also updated at boot loading. ff05h, default = 0000h 2.8.32 ecc result of 3 rd selected sector, spare area data register ff06h (r) this read register shows the error correction result for the 3rd selected sector of the spare area data. ecclogsector2 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. ec cposio2 is the error position address which selects 1 of 16 dq s. ecclogsector2 and eccposio2 are also updated at boot loading. ff06h, default = 0000h 2.8.33 ecc result of 4 th selected sector, main area data register ff07h (r) this read register shows the error correction result for the 4th selected sector of the main area data. eccposword3 is the erro r position address in the main area data of 256 words. eccposio3 is the error position address which selects 1 of 16 dqs. eccposword3 and eccposio3 are also updated at boot loading. ff07h, default = 0000h 2.8.34 ecc result of 4 th selected sector, spare area data register ff08h (r) this read register shows the error correction result for the 4th selected sector of the spare area data. ecclogsector3 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. ec cposio3 is the error position address which selects 1 of 16 dq s. ecclogsector3 and eccposio3 are also updated at boot loading. ff08h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword2 eccposio2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector2 eccposio2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword3 eccposio3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector3 eccposio3
onenand1gb(KFG1G16Q2C-xebx) flash memory - 62 - ecc log sector ecclogsector0~ecclogsector3 i ndicates the error position in the 2nd word and lsb of 3rd word in the spare area. refer to note 2 in chapter 2.7.2 ecclogsector information [5:4] ecclogsector error position 00 2nd word 01 3rd word 10, 11 reserved
onenand1gb(KFG1G16Q2C-xebx) flash memory - 63 - 3.0 device operation this section of the datasheet discusses the operation of the o nenand device. it is followed by ac/dc characteristics and timing diagrams which may be consulted for further information. the onenand supports a limited command-based interface in addition to a register-based interface for performing operations on t he device. 3.1 command based operation the command-based interface is active in the boot partition. comm ands can only be written with a boot area address. boot area d ata is only returned if no command has been issued prior to the read. the entire address range, except for the boot area, can be used for the data buffer. all commands are written to the boot parti tion. writes out- side the boot partition are treated as normal writes to the buffers or registers. the command consists of one or more cycl es depending on the command. after completion of the command the device starts its exec ution. writing incorrect information including address and data to the boot partition or writing an improper command will terminate th e previous com- mand sequence and make the device enter the ready status. the defined valid command sequences are stated in command sequences table. command based operations are mainly used when onenand is used as booting device , and all command based operations only supports asynchronous reads and writes. command sequences note : 1) bp(boot partition) : bootram area [0000h ~ 01ffh, 8000h ~ 800fh]. 2) load data into buffer operation is available within a block(128kb) 3) load 2kb unit into dataram0. current start address(fpa) is automatically incremented by 2kb unit after the load. 4) 0000h -> data is manufacturer id 0001h -> data is device id 0002h -> current block write protection status for mono chip 5) we toggling can terminate ?read identification data? operation. command definition cycles 1st cycle 2nd cycle reset onenand add 1 bp 1) data 00f0h load data into buffer 2) add 2 bp bp data 00e0h 0000h 3) read identification data 5) add 2 bp xxxxh 4) data 0090h data
onenand1gb(KFG1G16Q2C-xebx) flash memory - 64 - 3.1.1 reset onenand command the reset command is given by writing 00f0h to the boot partiti on address. reset will return all default values into the device . 3.1.2 load data into buffer command load data into buffer command is a two-cycle command. two sequent ial designated command activates this operation. sequentially writing 00e0h and 0000h to the boot partition [0000h~01ffh, 8000h~800fh] will lo ad one page to dataram0. this operation refers to fba a nd fpa. fsa, bsa, and bsc are not considered. at the end of this operation, fpa will be autom atically increased by 1. so continuous issue of this command will sequentially l oad data in next page to dataram0. this page address increment is restricted within a block. the default value of fba and fpa is 0. therefore, initial issue of this command after power on will load the first page of memo ry, which is usually boot code. 3.1.3 read identification data command the read identification data command consis ts of two cycles. it gives out the devices identification data according to the give n address. the first cycle is 0090h to the boot partition a ddress and second cycle is read from the a ddresses specified in identification data description ta b l e . identification data description note : 1) refer to device id register (chapter 2.8.3) 2)to read the write protection status, fba has to be set before issuing this command. address data out 0000h manufacturer id (00ech) 0001h device id 1) 0002h current block write protection status 2)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 65 - 3.2 device bus operation the device bus operations are shown in the table below. note : l=vil (low), h=vih (high), x=don?t care. operation ce oe we add0~15 dq0~15 rp clk avd standby h x x x high-z h x x warm reset xxxxhigh-zlxx asynchronous write l h l add. in data in h l x asynchronous read l l h add. in data out h l or l load initial burst read l h h add. in x h burst read l l h x burst data out h terminate burst read cycle hxhxhigh-zhxx terminate burst read cycle via rp xxxxhigh-zlxx terminate current burst read cycle and start new burst read cycle h h add in high-z h load initial burst write l h l add. in x h burst write l h x x burst data in hx terminate burst write cycle hxxxhigh-zhxx terminate burst write cycle via rp xxxxhigh-zlxx terminate current burst write cycle and start new burst write cycle h l add in high-z h x
onenand1gb(KFG1G16Q2C-xebx) flash memory - 66 - 3.3 reset mode operation the one nand has 4 reset modes: cold/warm/hot reset, and nand fl ash array reset. section 3.3 disc usses the operation of these r eset modes. the register reset table shows the which registers ar e affected by the various types or reset operations. internal register reset table note : 1a) rdypol, rdy conf, intpol, iobe are reset by cold re set. the other bits are reset by cold/warm/hot reset. 1b) the other bits except otp l and otp bl are reset by cold/warm/hot reset. 2) ecc status register & ecc result registers are reset when any command is issued. 3) refer to device id register f001h. 4) refer to version id register f002h. 5) resetting during idle state, this is valid. but resetting during busy state, refer to chapter 2.8.21. internal registers default cold reset warm reset (rp ) hot reset (00f3h) hot reset (bp- f0h) nand flash core reset (00f0h) f000h manufacturer id register (r) 00ech n/a n/a n/a n/a f001h device id register (r): onenand (note n/a n/a n/a n/a f002h version id register (r) (note n/a n/a n/a n/a f003h data buffer size register (r) 0800h n/a n/a n/a n/a f004h boot buffer size register (r) 0200h n/a n/a n/a n/a f005h amount of buffers register (r) 0201h n/a n/a n/a n/a f006h technology register (r) 0000h n/a n/a n/a n/a f100h start address1 register (r/w): fba 0000h 0000h 0000h 0000h n/a f101h start address2 register (r/w): reserved 0000h 0000h 0000h 0000h n/a f102h start address3 register (r/w): fcba 0000h 0000h 0000h 0000h n/a f103h start address4 register (r/w): fcpa, fcsa 0000h 0000h 0000h 0000h n/a f104h start address5 register (r/w): fpc 0000h 0000h 0000h 0000h n/a f107h start address8 register (r/w): fpa, fsa 0000h 0000h 0000h 0000h n/a f200h start buffer register (r/w): bsa, bsc 0000h 0000h 0000h 0000h n/a f220h command register (r/w) 0000h 0000h 0000h 0000h n/a f221h system configuration 1 register (r/w) 40c0h 40c0h (note1a) (note1a) n/a f240h controller status register (r) (note 1b) (note 5) 0000h 0000h 0000h 0000h n/a f241h interrupt status register (r/w) - 8080h 8010h 8010h n/a f24ch start block address (r/w) : sba 0000h 0000h 0000h n/a n/a f24dh end block address: n/a n/a n/a n/a n/a n/a f24eh nand flash write protection status (r) 0002h 0002h 0002h n/a n/a ff00h ecc status register (r) (note2) 0000h 0000h 0000h 0000h n/a ff01h ecc result of sector 0 main area data register(r) 0000h 0000h 0000h 0000h n/a ff02h ecc result of sector 0 spare area data register (r) 0000h 0000h 0000h 0000h n/a ff03h ecc result of sector 1 main area data register(r) 0000h 0000h 0000h 0000h n/a ff04h ecc result of sector 1 spare area data register (r) 0000h 0000h 0000h 0000h n/a ff05h ecc result of sector 2 main area data register(r) 0000h 0000h 0000h 0000h n/a ff06h ecc result of sector 2 spare area data register (r) 0000h 0000h 0000h 0000h n/a ff07h ecc result of sector 3 main area data register(r) 0000h 0000h 0000h 0000h n/a ff08h ecc result of sector 3 spare area data register (r) 0000h 0000h 0000h 0000h n/a
onenand1gb(KFG1G16Q2C-xebx) flash memory - 67 - 3.3.1 cold reset mode operation see timing diagram 6.15 at system power-up, the voltage detector in the device detects t he rising edge of vcc and releases an internal power-up reset s ignal. this trig- gers bootcode loading. bootcode loading means that the boot loader in the device copies designated sized data (1kb) from the be ginning of memory into the bootram. this sequence is the cold reset of onenand. the por(power on reset) triggering level is typically 1.5v. boot code copy operation activates typi cally 500us(max. 2ms) after por. therefore, the system power should reach 1.7v within 400us from the por triggering level for bootcode data to be valid. it takes typically 500us(max. 2ms) to copy 1kb of bootcode. upon co mpletion of loading into the bootram, it is available to be read by the host. the int pin is not available until afte r iobe = 1 and iobe bit can be changed by host. 3.3.2 warm reset mode operation see timing diagrams 6.16 a warm reset means that the host resets the device by using the rp pin. when the a rp low is issued, the device logic stops all current oper- ations and executes internal reset operation and resets current nand flash core oper ation synchronized with the falling edge of rp . during an internal reset operation, the device initializes internal registers a nd makes output signals go to default status. the bufferram data is kept unchanged after warm/hot reset operations. the device guarantees the logic reset operation in case rp pulse is longer than trp min(200ns). the device may reset if trp < trp min(200ns), but this is not guaranteed. warm reset will abort the current nand flas h core operation. during a warm reset, the content of memory cells being altered is no longer valid as the data will be partially programmed or erased. warm reset has no effect on contents of bootram and dataram. 3.3.3 hot reset mode operation see timing diagram 6.17 a hot reset means that the host resets the device by reset co mmand. the reset command can be either command based or register based. upon receiving the reset command, the device logic stop s all current operation and executes an internal reset operation and resets the current nand flash core operation. during an internal reset operation, the device initializes inte rnal registers and makes output signals go to default status. th e bufferram data is kept unchanged after warm/hot reset operations. hot reset has no effect on contents of bootram and dataram. 3.3.4 nand flash core reset mode operation see timing diagram 6.18 the host can reset the nand flash core operation by issuing a nand flash core reset command. nand flash core reset will abort the cur- rent nand flash core operation. during a na nd flash core reset, the content of memo ry cells being altered is no longer valid as the data will be partially programmed or erased. nand flash core reset has an effect on neither contents of bootram and dataram nor register values.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 68 - 3.4 write protection operation the onenand can be write-protected to prev ent re-programming or erasure of data. the areas of write-protection are the bootram, and the nand flash array. 3.4.1 bootram write protection operation at system power-up, voltage detector in the device detects t he rising edge of vcc and releases the internal power-up reset sign al which trig- gers bootcode loading. and the designated size da ta(1kb) is copied from the first page of the first block in the nand flash arr ay to the bootram. after the bootcode loading is completed, the bootram is alwa ys locked to protect the boot code from the accidental write. 3.4.2 nand flash array write protection operation the device has both hardware and software write protection of the nand flash array. hardware write protection operation the hardware write protection operation is im plemented by executing a cold or warm reset. on power up, the nand flash array is in its default, locked state. the entire nand flash array goes to a locked state after a cold or warm reset. software write protection operation the software write protection operation is implemented by writi ng a lock command (002ah) or a lock-tight command (002ch) to com mand register (f220h). lock (002ah) and lock-tight (002ch) commands write protects the block defined in th e start block address register f24ch. 3.4.3 nand array write pr otection states there are three lock states in the nand array: unlocked, locked, and locked-tight. onenand1gb supports lock/unlock/lock-tight by one block, and al l block unlock at once. if any blocks are changed to locked-tigh t state, the all block unlock command will fail. in order to use all block unlock command again, a cold reset is needed. write protection status the current block write protection status can be read in nand flas h write protection status register(f24eh). there are three bi ts - us, ls, lts -, which are not cleared by hot reset. these write protec tion status registers are updated when fba is set, and when write protection command is entered. the followings summarize locking status. example) in default, [2:0] values are 010. -> if host executes unlock bl ock operation, then [2:0] values turn to 100. -> if host executes lock-tight block operation, then [2:0] values turn to 001.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 69 - 3.4.3.1 unlocked nand array write protection state an unlocked block can be programmed or erased. the status of an unlocked block can be changed to locked or locked-tight using t he appro- priate software command. (locked-tight state can be ac hieved via lock-tight command which follows lock command) only one block can be released from lock state to unlock stat e with unlock command and addresses. the unlocked block can be cha nged with new lock command. therefore, each bloc k has its own lock/unlock/lock-tight state. if any blocks are changed to locked-tight state, the all block unl ock command will fail. in order to use all block unlock comma nd again, a cold reset is needed. 3.4.3.2 locked nand array write protection state a locked block cannot be programmed or erased. all blocks default to a locked state following a cold or warm reset. unlocked bl ocks can be changed to locked using the lock block command. the st atus of a locked block can be changed to unlocked or locked-tight using the appropriate software command. unlock command sequence: start block address+unlock block command (0023h) unlocked all block unlock command sequence: start block address(000h)+all block unlock command (0027h) note : even though sba is fixed to 000h, unlock will be done for all block. unlocked lock command sequence: start block address+lock block command (002ah) locked
onenand1gb(KFG1G16Q2C-xebx) flash memory - 70 - 3.4.3.3 locked-tight nand arra y write protection state a block that is in a locked-tight state can only be changed to lo cked state after a cold or warm reset. unlock and lock command sequences will not affect its state. this is an added level of write prot ection security. if any blocks are changed to locked-tight state , the all block unlock command will fail. in order to use all bloc k unlock command again, a cold reset is needed. a block must first be set to a locked state before it c an be changed to locked-tight using the lock-tight command. 3.4.4 nand flash array write protection state diagram *note : if the 1st block is set to be otp, block 0 will always be lock status lock-tight command sequence: start block address+lock-tight block command (002ch) locked-tight power on start block address +unlock block command rp pin: high & lock block command rp pin: high & +lock-tight block command rp pin: high & cold reset or unlock lock lock-tight lock lock warm reset start block address lock lock start block address cold reset or warm reset or unlock start block address (000h) rp pin: high & +all block unlock command
onenand1gb(KFG1G16Q2C-xebx) flash memory - 71 - data protection operation flow diagram note : 1) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 * samsung strongly recommends to follow the above flow chart start write ?lock/unlock/lock-tight? add: f220h dq=002ah/0023h/002ch write 0 to interrupt register 1) add: f241h dq=0000h command write ?sba? of flash add: f24ch dq=sba lock/unlock/lock-tight completed add: f240h dq[10]=0(pass) read controller status register add: f24eh dq[2:0]=us,ls,lts read write protection register wait for int register low to high transition add: f241h dq[15]=int write ?fba? of flash add: f100h dq=fba
onenand1gb(KFG1G16Q2C-xebx) flash memory - 72 - all block unlock flow diagram note : 1) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 * samsung strongly recommends to follow the above flow chart ** if any blocks are changed to locked-tight st ate, the all block unlock command will fail. in order to use all block unlock command again, a cold reset is needed. start write ?all block unlock? add: f220h dq=0027h wait for int register low to high transition add: f241h dq[15]=int command write 0 to interrupt register 1) add: f241h dq=0000h write ?sba? of flash add: f24ch dq=sba(000h) unlock all block completed add: f240h dq[10]=0(pass) read controller status register add: f24eh dq[2:0]=us,ls,lts read write protection register write ?fba? of flash add: f100h dq=fba
onenand1gb(KFG1G16Q2C-xebx) flash memory - 73 - 3.5 data protection duri ng power down operation see timing diagram 6.19 the device is designed to offer protection from any involuntary program/erase during power-transitions. rp pin which provides hardware prot ection is recommended to be kept at vil before vcc drops to 1.5v. 3.6 load operation see timing diagrams 6.12 the load operation is initiated by setting up the start address fr om which the data is to be loaded. the load command is issued in order to ini- tiate the load. during a load operation, the device: -transfers t he data from nand flash array into the bufferram -ecc is checked and any detected and corrected error is reported in the status response as well as any unrecoverable error. once the bufferram has been filled, an interrupt is issued to the host so that the contents of the bufferram can be read. the r ead from the bufferram can be an asynchronous read mode or synchronous read m ode. the status information related to load operation can be ch ecked by the host if required. the device has a dual data buffer memory architecture (dataram 0, dataram1), each 2kb in size. each dataram buffer has 4 sectors. the device is capable of independent and simultaneous data-read operation from one data buffer and data-load operation to the other data buffer. refer to the information for more details in section 3.12.1, "read-while-load operation". load operation flow chart diagram note : 1) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int read controller add: f240h dq[10]=error dq[10]=0? no yes status register host reads data from dataram read completed map out write 0 to interrupt register 1) add: f241h dq=0000h
onenand1gb(KFG1G16Q2C-xebx) flash memory - 74 - 3.7 read operation see timing diagrams 6.1, 6.2, 6.5, 6.6, 6.7 and 6.8 the device has two read modes; asynchronous read and synchronous burst read. the initial state machine automatically sets the device into t he asynchronous read mode (rm=0) to prevent the spurious altering of memory content upon device power up or after a hardware reset. no commands are required to retrieve data in asynchronous read mode. the synchronous read mode is enabled by setting rm bit of system configuration1 regist er (f221h) to synchronous read mode (rm=1 ). see section 2.8.19 for more information about system configuration1 register. 3.7.1 asynchronous read mode operation (rm=0, wm=0) see timing diagrams 6.5, 6.6, 6.7 and 6.8 in an asynchronous read mode, data is out put with respect to a logic input, avd . output data will appear on dq15-dq0 when a valid ad dress is asserted on a15-a0 while driving avd and ce to vil. we is held at vih. the function of the avd signal is to latch the valid address. address access time from avd low (taa) is equal to the delay from valid addresses to valid output data. the chip enable access time (tce) is equal to the delay from the falling edge of ce to valid data at the outputs. the output enable access time (toe) is the delay from the falling edge of oe to valid data at the output. 3.7.2 synchronous read mode operation (rm=1, wm=x) see timing diagrams 6.1 and 6.2 in a synchronous read mode, data is out put with respect to a clock input. the device is capable of a continuous li near burst operation and a fixed-length linear burst operation of a preset length. bur st address sequences for continuous and fixed-length bur st operations are shown in the table below. burst address sequences in the burst mode, the initial word will be output asynchronously , regardless of brwl. while the following words will be determ ined by brwl value. the latency is determined by the host based on the brwl bit setti ng in the system configuration 1 register. the default brwl is 4 latency cycles. at clock frequencies of 40mhz or lower, latency cycles can be reduced to 3. brwl can be set up to 7 latency cycles. the brwl registers can be read during a burst read mode by using the avd signal with an address. start addr. burst address sequence(decimal) continuous burst 4-word burst 8-word burst 16-word burst 32-word burst wrap around 0 0-1-2-3-4-5-6-..-0-1... 0-1-2-3-0... 0-1-2-3-4-5-6-7-0... 0-1-2-3-4-....-13-14-15-0... 0-1-2-3-4-....-29-30-31-0... 1 1-2-3-4-5-6-7-..-1-2... 1-2-3-0-1... 1-2-3-4-5-6-7-0-1... 1-2-3-4-5-....-14-15-0-1... 1-2-3-4-5-....-30-31-0-1... 2 2-3-4-5-6-7-8-..-2-3... 2-3-0-1-2... 2-3-4-5-6-7-0-1-2... 2-3-4-5-6-....-15-0-1-2... 2-3-4-5-6-....-31-0-1-2... . . . . . . . . . . . .
onenand1gb(KFG1G16Q2C-xebx) flash memory - 75 - 3.7.2.1 continuous linear burst read operation see timing diagram 6.2 first clock cycle the initial word is output at tiaa after the rising edge of the fi rst clk cycle. the rdy output indicates the initial word is r eady to the system by pulsing high. if the device is ac cessed synchronously while it is set to asynch ronous read mode, the first data can still be re ad out. subsequent clock cycles subsequent words are output (burst access time from valid cloc k to output) tba after the rising edge of each successive clock c ycle, which automatically increments the internal address counter. terminating burst read the device will continue to output sequenti al burst data until the system asserts ce high, or rp low, wrapping around until it reaches the des- ignated address (see section 2.7.3 for address map information). alternately, a cold/warm/hot reset, or a we low pulse will terminate the burst read operation. synchronous read boundary * reserved area is not available on synchronous read 3.7.2.2 4-, 8-, 16-, 32-word linear burst read operation see timing diagram 6.1 an alternate burst read mode enables a fixed number of words to be read from consecutive address. the device supports a burst read from consecutive addresses of 4-, 8-, 16-, and 32-words with a linear-wrap around. when the la st word in the burst has been reached, assert ce and oe high to terminate the operation. in this mode, the start address for the burst read can be any ad dress of the address map with one exception. the device does no t support a 32-word linear burst read on the spare area of the bufferram. division add.map(word order) bootram main(0.5kw) 0000h~01ffh bufferram0 main(1kw) 0200h~05ffh bufferram1 main(1kw) 0600h~09ffh reserved main 0a00h~7fffh bootram spare(16w) 8000h~800fh bufferram0 spare(32w) 8010h~802fh bufferram1 spare(32w) 8030h~804fh reserved spare 8050h~8fffh reserved register 9000h~efffh register(4kw) f000h~ffffh not support not support not support not support not support
onenand1gb(KFG1G16Q2C-xebx) flash memory - 76 - 3.7.2.3 programmable burst read latency operation see timing diagrams 6.1 and 6.2 upon power up, the number of initial clock cycles from valid address (avd ) to initial data defaults to four clocks. the number of clock cycles (n) which are inserted after the clock which is latc hing the address. the host can read the first da ta with the (n+1)th rising edge. the number of total initial acce ss cycles is programmabl e from three to seven cycles. after the number of programmed burst cloc k cycles is reached, the rising edge of the next cloc k cycle triggers the next burst data. four clock burst read latency (brwl=4 case) *note : brwl=4, hf=0 is recommended for 40mhz~66mhz. for fre quency over 66mhz, brwl should be 6 or 7 while hf=1. also, for frequency under 40mhz, brwl can be reduced to 3, and hf=0. 3.7.3 handshaking operation the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial w ord of burst data is ready to be read. to set the number of initial cycles for optimal burst mode, t he host should use the programmable burst read latency configurati on (see section 2.8.19, "system configuration1 register"). the rising edge of rdy which is derived at one cycle prior of data fetch clock indicates the initial word of valid burst data. 3.7.4 output disable mode operation when the ce or oe input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. t iaa hi-z ce clk avd oe rdy t rdys t rdya dq0: dq15 d6 d7 d0 d1 d2 d3 d7 d0 hi-z 0123 -1 t ba rising edge of the clock cycle following last read latency triggers next burst data a0: a15 valid address 4
onenand1gb(KFG1G16Q2C-xebx) flash memory - 77 - 3.8 cache read oper ation (rm=x, wm=x) a normal load operation(0000h) consists of sequential operation of ?sensing from nand flash array to page buffer? and ?transfer ring from page buffer to dataram?. cache read is a method of improving the data read throughput perf ormance of the device by allowing new data to be transferred f rom the nand flash array memory into a page buffer while the previous da ta that was requested is transferred from the page buffer to th e dataram. this method is called transfe r-while sensing operation. this ability to simultaneously sense a new page shortens the read cycle resulting in performance increase to 108mbytes/second. cache read mode is designed to cont inuously read massive data from random address at a high speed. the characteristics of ca che read is as follows; -before entering ?first cache read command( 000eh)?, address of two pages which will be read will be set on address registers. t he register information follows on next line. -register used for first page is copy-back registers (fcba, fcpa and fcsa). and the registers used for addressing second page a nd follow- ing cache read are normal address registers(fba, fpa and fsa). at cache read operation, fcsa and fsa must be set to "00". -bsa setting is only required once at ?first cache read? cycle. fr om the following cycles, bsa will be automatically switched t o select dataram0 and dataram1 alternately. -bsc must be fixed as "00" -to eliminate performance degradation during ready state(int high state) due to register setting time, setting registers (fba, fpa and fsa) during busy state(int low state) is pos sible from third address setting onwards. -inputting other commands, which is not related to cache read, between ?first cache read command? and ?finish cache read comman d? will fail the cache read operation. -in case of performing cache read at int auto mode, int low setti ng is not necessary. int will automatically go to low when cac he read command is issued. transfer-while sensing operation a cache-read flow chart is on the following page. dataram page buffer selected page nand flash array 1) sensing 1) transfer 2) read host
onenand1gb(KFG1G16Q2C-xebx) flash memory - 78 - cache read flow chart note : 1) in case of first cycle cache read, bsa must be set to 1000 or 1100, and from second cycle cache read, bsa will automatically be switched between dataram0 and dataram1. 2) bsc, fsa and fcsa must be set to "00". 3) these steps can also be set during int=high, before next ?cache read command? 4) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 5) when host reads data from dataram, host should start from the dataram of the first set bsa, and then next dataram alternately, as the number of cache read. start write ?fcba? of flash add: f102h dq=fcba write ?fcpa, fcsa 2) ? of flash add: f103h dq=fcpa, fcsa write ?bsa 1) , bsc 2) ? of flash add: f200h dq=bsa, bsc write ?fpa, fsa 2) ? of flash add: f107h dq=fpa, fsa write ? cache read? command add: f220h dq=000eh map out write 0 to interrupt register 4) add: f241h dq=0000h write ?fpa, fsa 2) ? of flash 3) add: f107h dq=fpa, fsa end add: f220h dq=000ch host reads data from dataram 6) wait for int high state add: f241h dq[15]=int read controller status add: f240h dq[10]=error register dq[10]=0? yes no host reads data from dataram write ?finish cache read command? @ final read write ?fba? of flash add: f100h dq=fba write ?fba? of flash 3) add: f100h dq=fba read controller status dq[15]=ongo & dq[13]=load register add: f240h dq[15]=1 & dq[13]=1 ? yes no wait for int high state add: f241h dq[15]=int read controller status add: f240h dq[10]=error register dq[10]=0? yes write 0 to interrupt register 4) add: f241h dq=0000h host reads data from dataram 5) no done with no yes (n-1)th command issue? write ? cache read? command add: f220h dq=000eh wait for int high state add: f241h dq[15]=int read controller status add: f240h dq[10]=error register dq[10]=0? yes write 0 to interrupt register 4) add: f241h dq=0000h no
onenand1gb(KFG1G16Q2C-xebx) flash memory - 79 - cache read diagram int add/ 1st address host reads 1st data from dataram setting 2nd address setting command setting 4th address setting command setting status read status read host reads (n-2)th data from dataram command setting status read host reads (n-1)th data from dataram command setting status read finish host reads nth data from dataram -1st address setting : address setting operation for first page load(fcba, fcpa, fcsa, and bsa). -2nd~nth address setting : address setting operation from 2nd~nth page load(fba and fpa). -command setting : it consists of writing 0 to interrupt register and writing command to command register. (in int auto mode, writing 0 to interrupt register may be ignored) -status read : it consists of int high state c hecking and controller status register checking step. -host read 1st~nth data from dataram : during this step, host c an read data from dataram by any read mode which supported by on enand. -finish command setting : if host want to finish cache read, host can finish cahce read by issuing finish command. -controller status register status: during cache read - ongoing / load ecc error during cache read - ongoing / load / error ecc error at finish cache read - load / error note : 1) 3rd~nth address can be set during int=low, and also during int=high, before next ?cache read command?. dq int add/ 0~15 dq 0~15 (cont.) (cont.) 3rd address setting 1)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 80 - 3.9 synchronous burst block r ead operation (rm=1,wm=x) see timing diagram 6.3 and 6.4 onenand is internally composed of two data rams and nand flash array. and for host to read data from nand cell array, load opera tion which moves data from nand cell array to dataram is required. after this load operation, host may use various read mode, such a s synchronous burst read or asynchronous read, to read data from onenand. but these types of read mode require issuing of address and load command for each page, and cpu had the burden of calculating a ddress to be read. to solve this burden, synchronous burst block read mode is introduced, which enables host to read the data of succe eding page with clk toggle, after initial address setting and command input. this synchronous burst block read is intended to transfer con tinuous mas- sive data in nand flash array at high speed, and it sequentially r eads out data only from main area, where large sized data is stored. the addresses set for synchronous burst block read is start page address(fp a), number of page(fpc) and bsa. note that the numbe r of page set by fpc should not exceed the bl ock boundary, since page wrap-around is not supported. and from the start page address to desired number of page, synchronous burst block read will output data by clk toggle and ce enable/disable. fpc must be set from 3pages to 64pages. (refer to 2.8.13) the host can access onenand during synchr onous burst block read in between every 1-pa ge of read cycle. when host accesses dat- arams, the address of datarams must be a multiple of 4 in order to prevent from data corruption. in doing this, int pin or bit is used as indi- cator signal. thus, before host reads 1-page data from dataram, hos t must confirm int pin or bit return low to high, and then enable ce to read 1-page of data. and when host read operation for this 1-page is done, int will automatically turn low. note that int auto mode is a man- datory option for synchronous burst block read, and we must always be set high throughout this opeartion. therefore, the steps are as follows; 1. host will deassert ce of onenand after checking the i ndicator(int pin / bit) turn low. 2. and then assert the ce of other device to perform another operation. 3. then disable this other device by deasserting ce when desired operation is done. 4. once the host confirms the int pin or bit of onenand turn low to high, host may read the data of following page by asserting ce (refer to synchronous burst block read operation timing). note that return of int pin to high implies the internal load operation from nand flash array to dataram is complete. also, eve n when the host is not accessing other device, this assert/deassert of ce step is neccessary. note that return of int pin to high implies the internal load oper ation from nand flash array to dataram is complete. also, whe n the host is not accessing other device, this assert/deassert of ce step is neccessary. to read data from this loaded 1 page, same 4, 8, 16, 32, c ontinuous (1k word) linear burst read operation of synchronous burst read may be utilized. in conclusion, by supporting indicator signal such as int pin or bit, host may access other device without terminating continuo us linear syn- chronous burst block read, while using continuous linear burst read mode as syn chronous block read within 1 block between every (n) page and (n+1) page. (refer to synchronous burst block read boundary)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 81 - 3.9.1 burst address sequence during synchronous burst block read mode in a synchronous burst block read, data is output with respect to a clock input. onenand is capable of a continuous linear burst operation wi thin one block size and a fixed-l ength linear burst operation of a preset length. note that only int pin is valid indicator signal for continuous linear burst read operation but both int pin and bit are valid for a fixed-length lin- ear burst operation. same as the normal burst mode, the initial word will be output as ynchronously, regardless of brwl while the following words wil l be deter- mined by brwl value. the latency is determined by the host based on the brwl bit setti ng in the system configuration 1 register. the default brwl is 4 latency cycles. at clock frequencies of 40mhz or lowe r, latency cycles can be reduced to 3, at frequency range from 40mhz to 66mhz, lat ency cycle should be over 4. and at 83mhz frequency, brwl should be set to 6. brwl can be set up to 7 latency cycles. the brwl registers can be read during a burst read mode by using the avd signal with an address. 3.9.2 continuous linear burst read operation during synchronous burst block read mode first clock cycle the initial word is output at tiaa after the rising edge of the fi rst clk cycle. the rdy output indicates the initial word is r eady to the system by pulsing high. if the device is ac cessed synchronously while it is set to asynch ronous read mode, the first data can still be re ad out. subsequent clock cycles subsequent words are output (burst access time from valid cloc k to output) tba after the rising edge of each successive clock c ycle, which automatically increments the internal address counter. terminating synchronous burst block read the device will continue to output sequential burst data until the system resets (cold/warm/hot reset), wrapping around until i t reaches the designated address (see section 3.9.1 for burst address sequence). asserting we low is prohibited during synchronous burst block read operation.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 82 - synchronous burst block read boundary read sequence for single plane device note that only main area data is read. main area { spare area page 0 page 63 . . . not supported
onenand1gb(KFG1G16Q2C-xebx) flash memory - 83 - 3.9.3 4-, 8-, 16-, 32-, 1k- word linear burst read operation during synchronous burst block read mode same as normal linear burst read, synchron ous burst block read enables a fixed number of words to be read from consecutive addr ess. the device supports a burst read from consecutive add resses of 4-, 8-, 16-, 32- and 1k-words with no wrap. (note that wrap-around is not supported in synchronous burst block read) 3.9.4 programmable burst read latency operation during synchronous burst block read mode synchronous burst block read mode have progrmmable burst read latency just same manner as normal synchronous burst read mode. upon power up, the number of initial clock cycles from valid address (avd ) to initial data defaults to four clocks. the number of clock cycles (n) which are inserted after the clock which is latc hing the address. the host can read the first da ta with the (n+1)th rising edge. the number of total initial acce ss cycles is programmabl e from three to seven cycles. after the number of programmed burst cloc k cycles is reached, the rising edge of the next cloc k cycle triggers the next burst data. four clock burst read latency (default condition) t iaa hi-z ce clk avd oe rdy t rdys t rdya dq0: dq15 d6 d7 d0 d1 d2 d3 d7 d0 hi-z 0123 -1 t ba rising edge of the clock cycle following last read latency triggers next burst data a0: a15 valid address 4
onenand1gb(KFG1G16Q2C-xebx) flash memory - 84 - 3.9.5 handshaking operation during synchronous burst block read mode the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial w ord of burst data is ready to be read. to set the number of initial cycles for optimal burst mode, t he host should use the programmable burst read latency configurati on (see section 2.8.19, "system configuration1 register"). the rising edge of rdy which is derived at one cycle prior of data fetch clock indicates the initial word of valid burst data. synchronous burst block read operation flow chart note : 1) these registers must be set as bsa=1000, bsc=00 and fsa=00. 2) int auto mode is mandatory for synchronous burst block read operation. 3) for the continuous synchronous burst block read, only int pi n is availabe. for the other fixed number of words linear burst block read, both int register and int pin are avilable. 4) while reading data from dataram, all normal synchronous burst read mode is supported for the main area. 5) at this time, host should disable the ce of onenand in order to operate another device. even if host does not operate another device, ce should be disabled during int low. write ?fba? of flash add: f100h dq=fba start write ?fpa, fsa? of flash add: f107h dq=fpa, fsa 1) write ?fpc? of flash add: f104h dq=fpc write synchronous burst add=f220h dq=000ah block read command wait for int register or pin 3) low to high transition add: f241h dq[15]=int host reads data from dataram 0 4) wait for int register or pin 3) high to low transition add: f241h dq[15]=int host may operate another device while ce of onenand is disabled 5) wait for int register or pin 3) low to high transition add: f241h dq[15]=int wait for int register or pin 3) high to low transition add: f241h dq[15]=int host may operate another device while ce of onenand is disabled 5) wait for int register or pin 3) low to high transition add: f241h dq[15]=int finished reading final page set by fpc? yes read controller status register add: f240h dq[10]=1(error) synchronous burst block dq[10]=0? yes no read completed synchronous burst block read fail no finished reading final page set by fpc? yes host reads data from dataram 1 4) host reads data from dataram 0 4) no write ?bsa*, ?bsc? of flash 1) add: f200h dq=bsa, bsc write 0 to int register or pin 2)3) add: f241h dq=0000h
onenand1gb(KFG1G16Q2C-xebx) flash memory - 85 - 3.10 synchronous write(rm=1, wm=1) see timing diagram 6.10 burst mode operations enable high-speed synchr onous read and write operations. burst operat ions consist of a multi-clock sequen ce that must be performed in an ordered fashion. after ce goes low, the address to access is latched on the next rising edge of clk that adv is low. during this first clock rising edge, we indicates whether the operation is going to be a read (we = high) or write (we = low). the size of a burst can be specified in the bl as eit her a fixed length or continuous. fixed-lengt h bursts consist of 4, 8, 16, and 32 words. continuous burst write has the ability to start at a specified address and burst wi thin the designated dataram. the latency count stored in the brwl defines the number of clock cycles that elapse before the initial data value is transferred between the processor and onenand device. the rdy output will be asserted as soon as a burst is initiat ed, and will be de-asserted to indicate when data is to be transfe rred into (or out of) the memory. the processor can access ot her devices without incurring the timing penalty of the initial latency for a new bu rst by suspend- ing burst mode. bursts are suspended by stopping clk. clk can be stopped high or low. note that the rdy output will continue to be active, and as a result no other devices should directly share the rdy connection to the controller. to continue the burst sequence, clk is restar ted after valid data is available on the bus. same as the normal burst mode, the latency is determined by t he host based on the brwl bit setting in the system configuration 1 register. the default brwl is 4 latency cycles. at cl ock frequencies of 40mhz or lower, latenc y cycles can be reduced to 3, at frequency range from 40mhz to 66mhz, latency cycle should be over 4. and at 83mhz frequency, brwl should be set to 6. brwl can be set up to 7 latenc y cycles.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 86 - 3.11 program operation see timing diagram 6.13 the program operation is used to program data from the on-chip bufferrams into the nand flash memory array. the device has two 2kb data buffers, each 1 page (2kb + 64b) in size. each page has 4 sectors of 512b each main area and 16b sp are area. the device can be programmed in units of 1~4 sectors. the architecture of the datarams permits a simultaneous data-w rite operation from the host to one of data buffers and a program operation from the other data buffer to the nand flash array memory. refer to section 3.12.2, "write while program operation", for more i nformation. addressing for program operation within a block, the pages must be programm ed consecutively from the lsb (least signif icant bit) page of the block to msb (most significant bit) pages of the block. random page address programming is prohibited from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 : : : :
onenand1gb(KFG1G16Q2C-xebx) flash memory - 87 - program operation flow diagram note : 1) data input could be done anywhere between "start" and "write program command". 2) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 . during the execution of the internal program routine, the host is not required to provide any fu rther controls or timings. furt hermore, all com- mands, except a reset command, will be ignored. a reset during a program operation will cause data corruption at the correspond ing location. if a program error is detected at the completion of the internal program routine, map out the block, including the page in err or, and copy the target data to another block. an error is signaled if dq10 = "1" of controller status register(f240h) . data input from the host to the dataram can be done at any time during the internal program routine after "start" but before th e "write pro- gram command" is written. start data input write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write data into dataram 1) add: dp dq=data-in program completed write ?program? command add: f220h dq=0080h or 001ah completed? wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? program error yes no no yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * write 0 to interrupt register 2) add: f241h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc read interrupt register add: f241h dq[6]=wi dq[6]=1? yes no add: f240h dq[14]=lock read controller status register ?lock? bit high program lock error
onenand1gb(KFG1G16Q2C-xebx) flash memory - 88 - 3.12 copy-back program operation the copy-back program is configured to qui ckly rewrite data stored in one page without utilizing memory other than onenand. sin ce the time-consuming cycles of serial access and re-loading cycles are removed, the sy stem performance is improved. the benefit is es pecially obvious when a portion of block is updated and the rest of th e block also need to be copied to the newly assigned free block. data from the source page is saved in one of the on-chip data ram buffers and then programmed directly into the destination page . the dat- aram is overwritten the previous data using the buffer sector addre ss (bsa) and buffer sector count (bsc). the copy-back program operation does this by performing sequential page-reads without a serial acce ss and executing a copy-prog ram using the address of the destination page. copy-back program operation flow chart note : 1) selected dataram by bsa & bsc is used for copy back operation, so previous data is overwritten. 2) fba, fpa and fsa should be input prior to fcba, fcpa and fcsa. 3) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?fcba? of flash add: f102h dq=fcba write ?fcpa, fcsa? of flash add: f103h dq=fcpa, fcsa copy back completed write ?copy-back program? command add: f220h dq=001bh wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? copy back error yes no : if program operation r esults in an error, map out the block including the page in error and copy the target data to another block. * write 0 to interrupt register add: f241h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc 1)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 89 - the copy-back steps shown in the flow chart are: ? data is read from the nand array using flash block address (fba), flash page address (fpa) and flash sector address (fsa). fba, fpa, and fsa identify the source address to read data from nand flash array. ? the bufferram sector count (bsc) and bufferram se ctor address (bsa) ident ifies how many sectors and the location of the sectors in dataram that are used. ? the destination address in the nand array is written using the flash copy-bac k block address (fcba), flash copy-back page addr ess (fcpa), and flash copy-back sector address (fcsa). ? the copy-back program command is issued to start programming. ? upon completion of copy-back programming to the dest ination page address, the host checks the status to see if the operation was successfully completed. if there was an error, map out the block including the page in error and copy the target data to another block.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 90 - 3.12.1 copy-back program operation with random data input the copy-back program operation with random data input in onen and consists of 2 phase, load data into dataram, modify data and pro- gram into designated page. data from the source page is saved in one of the on-chip dataram buffers and modified by the host, t hen pro- grammed into the destination page. as shown in the flow chart, data modificati on is possible upon completion of load operati on. ecc is also available at the end o f load operation. therefore, using hardware ecc of onenand, accumulation of 1 bit error can be avoided. copy-back program operation with random data input will be effectively utilized at modifying certain bit, byte, word, or sector of source page to destination page while it is being copied. copy-back program operation with random data input flow chart note : 1) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int read controller add: f240h dq[10]=error status register write 0 to interrupt register 1) add: f241h dq=0000h dq[10]=0? no yes map out copy back completed wait for int register low to high transition add: f241h dq[15]=int copy back error random data input write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?program? command add: f220h dq=0080h or 001ah write 0 to interrupt register add: f241h dq=0000h add: random address in selected dataram dq=data read interrupt register add: f241h dq[6]=wi dq[6]=1? yes add: f240h dq[10]=error read controller status register dq[10]=0? yes no no add: f240h dq[14]=lock read controller status register ?lock? bit high copy back program lock error
onenand1gb(KFG1G16Q2C-xebx) flash memory - 91 - 3.13 erase operation there are multiple methods for erasing data in the device including block er ase and multi-block erase. 3.13.1 block erase operation see timing diagram 6.14 the block erase operation is done on a block bas is. to erase a block is to write all 1's into the desired memory block by execu ting the internal erase routine. all pr evious data is lost. block erase operation flow chart note : 1) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 : if erase operation results in an error, map out the failing block and replace it with another block. * start write ?fba? of flash add: f100h dq=fba write ?erase? command add: f220h dq=0094h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register 1) add: f241h dq=0000h read interrupt register add: f241h dq[5]=ei dq[5]=1? yes add: f240h dq[10]=error read controller status register erase completed dq[10]=0? yes erase error no add: f240h dq[14]=lock read controller status register ?lock? bit high erase lock error no
onenand1gb(KFG1G16Q2C-xebx) flash memory - 92 - in order to perform the internal erase routine, the following command sequence is necessary. ? the host sets the block address of the memory location. ? the erase command initiates the internal erase routine. during the execution of the routine, the host is not required to provide further controls or timings. during the internal erase routine, all commands, except the reset command and erase su spend command, written to the device will be ignored. a reset during an erase operation will cause data corruption at the corresponding location. 3.13.2 multi-block erase operation see timing diagram 6.14 using multi-block erase, the device can be erased up to 64 multiple blocks simultaneously. multiple blocks can be erased by issuing a multi-block erase command and writing the block address of the memory location to be erased. the final flash block address (fba) and bloc k erase command initiate the internal multi block erase routine. during a multi-blo ck erase, the ongo bit of the controller status register is set to '1'(busy) from the time that the first block address to be latched is writ ten to the time that the actual erase operation finishes. during block address latch sequence, issuing of other commands except block eras e, and multi block erase at int=high will abort the current operation. so to speak, it will cancel the previous ly latched addresses of multi block erase operation. on the other hand, other command issue at int=low will be ignored. a reset during an erase operation will cause data corrupti on at the address location being operated on during the reset. despite a failed block during multi-block er ase operation, the device will continue t he erase operation until all other specifi ed blocks are erased. erase suspend command issue during multi bloc k erase address latch sequence is prohibited. locked blocks if there are locked blocks in the specified range, t he multi-block erase operation works as the follows. case 1: all specified blocks except ba(2) will be erased. [ba(1)+0095h] + [ ba((2), locked)) +0095h] + ... + [ba(n-1)+0095h] + [ba(n)+0094h] case 2: multi-block erase operation fails to start if the la st block erase command is put together with the locked block addres s until right com- mand and address input are issued. [ba(1)+0095h] + [ba(2)+0095h] + ... + [ba(n-1)+0095h] + [ ba((n), locked) +0094h] case 3: all specified bloc ks except ba(n) are erased. [ba(1)+0095h] + [ba(2)+0095h] + ... + [ba(n-1)+0095h] + [ ba(n, locked) +0094h] + [ba(n+1)+0094h]
onenand1gb(KFG1G16Q2C-xebx) flash memory - 93 - 3.13.3 multi-block erase verify read operation after a multi-block erase operation, verify erase operation result of each block wi th multi-block erase verify command combined with address of each block. if a failed address is identified, it must be managed by firmware. multi block erase/ multi block erase verify read flow chart note : 1) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 add: f240h dq[10]=0 read controller status register start write ?fba? of flash add: f100h dq=fba write ?multi block erase? add: f220h dq=0095h wait for int register add: f241h dq[15]=int final multi block yes no low to high transition write 0 to interrupt register add: f241h dq=0000h command erase? write ?fba? of flash add: f100h dq=fba write ?block erase add: f220h dq=0094h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register 2) add: f241h dq=0000h command? multi block erase verify read write ?fba? of flash add: f100h dq=fba write ?multi block erase add: f220h dq=0071h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h verify read command? read controller add: f240h dq[10]=error status register dq[10]=0? multi block erase completed final multi block yes no erase address? erase completed no read interrupt register add: f241h dq[5]=ei dq[5]=1? yes add: f240h dq[14]=lock read controller status register ?lock? bit high multi block erase lock/ no erase lock error no read interrupt register add: f241h dq[5]=ei dq[5]=1? yes add: f240h dq[10]=0 read controller status register erase error yes
onenand1gb(KFG1G16Q2C-xebx) flash memory - 94 - 3.13.4 erase suspend / erase resume operation the erase suspend/erase resume commands interrupt and restart a block erase or multi-block eras e operation so that user may per form another urgent operation on the block that is not being designated by erase/mult i-block erase operation. erase suspend during a block erase operation when erase suspend command is written during a block erase or multi-block erase operat ion, the device requires a maximum of 500 us to suspend erase operation. erase suspend command issue during block address latc h sequence is prohibited. after the erase operation has been suspended, the device is ready for the next operati on including a load, program, copy-back p rogram, lock, unlock, lock-tight, hot reset, nand flash core reset, command based reset, multi-block erase read verify, or otp access. the subsequent operation can be to an y block that was not being erased. a special case arises pertaining erase suspend to the otp. a reset command is used to exit from the otp access mode. if the re set-trig- gered exit from the otp access mode happens during an erase suspend operation, the erase routine c ould fail. therefore to exit from the otp access mode without suspending the erase operation stop, a 'nand flash core reset' command should be issued. for the duration of the erase suspend period the following commands are not accepted: ? block erase/multi-block erase/erase suspend erase suspend and erase resume operation flow chart note : 1) erase suspend command input is prohibited during multi block erase address latch period. 2) if otp access mode exit happens with reset operation during erase suspend mode, reset operation could hurt the erase operation. so if a user wants to exit from otp access mode without the erase operation stop, rese t nand flash core command should be used. 3) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start write ?erase suspend add: f220h dq=00b0h wait for int register add: f241h dq=[15]=int low to high transition for 500us command? 1) write 0 to interrupt register 3) add: f241h dq=0000h write ?erase resume add: f220h dq=0030h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register 3) add: f241h dq=0000h command? another operation * * another operation ; load, program copy-back program, otp access 2) , hot reset, flash reset, cmd reset, multi block erase verify, lock, lock-tight, unlock check controller status register do multi block erase verify read in case of block erase in case of multi block erase
onenand1gb(KFG1G16Q2C-xebx) flash memory - 95 - erase resume when the erase resume command is executed, t he block erase will restart. the erase resume operation does not actually resume th e erase, but starts it again from the beginning. when an erase suspend or erase resume command is ex ecuted, the addresses are in don't care state. for multi block erase, erase suspend/resume can be operated afte r final erase command (0094h) is issued. therefore, erase resum e oper- ation does not actually resume from the erased block, but resumes the multi block erase from the beginning. 3.14 otp operation one block of the nand flash array memory is rese rved as a one-time programmable block memory area. also, 1st block of nand flash array can be used as otp. the otp block can be read, programmed and locked using the same operations as any other nand flash array memory block. otp block cannot be erased. otp block is fully-guaranteed to be a valid block. entering the otp block the otp block is separately accessible from the rest of the na nd flash array by using the otp access command instead of the fla sh block address (fba). exiting the otp block to exit the otp access mode, a cold-, warm-, hot-, or nand flash core reset operation is performed. exiting the otp block during an erase operation if the reset-triggered exit from the otp access mode happens dur ing an erase suspend operation, t he erase routine could fail. t herefore to exit from the otp access mode without suspending the erase operati on stop, a 'nand flash core reset' command should be issued. the otp block page assignments otp area is one block size (128kb+4kb, 64 pages) and is divided in to two areas. the 50-page user area is available as an otp st orage area. the 14-page manufacturer area is programmed by the manufacturer prior to shipping the device to the user. otp block page allocation information three possible otp lock sequence (refer to chapter 3.14.3~3.14.5 for more information) since otp block and 1st block otp can be lock ed only by programming into 8th word of sector0, page0 of the spare memory area of otp, otp block and 1st block otp lock sequence is restricted into three following cases. note that user should be careful, because locking otp block before locking 1st block otp will disable locking 1st block otp. 1. otp block lock only : once the otp block is locked, 1st block otp lock is impossible. 2. 1st block otp lock, and then lock otp block afterwards : locking 1st block otp does not lock the otp block, so that otp block lock can be performed thereafter. 3. otp block lock and 1st block otp lock simultaneously: this simultaneous operation can be done by pr ogramming into 8th word of sector0, page0 of the spare memory area o f otp. area page use user 0 ~ 49 (50 pages) designated as user area manufacturer 50 ~ 63 (14 pages) used by the device manufacturer
onenand1gb(KFG1G16Q2C-xebx) flash memory - 96 - otp block area structure 1st block otp area structure page:2kb+64b sector(main area):512b sector(spare area):16b one block: 128kb+4kb 64pages manufacturer area : page 50 to page 63 14pages user area : page 0 to page 49 50pages page:2kb+64b sector(main area):512b sector(spare area):16b one block: 128kb+4kb 64pages user area : page 0 to page 63 64pages
onenand1gb(KFG1G16Q2C-xebx) flash memory - 97 - 3.14.1 otp block load operation an otp block load operation accesses the otp area and transfers i dentified content from the otp to the dataram on-chip buffer, thus making the otp contents available to the host. the otp area is a separate part of the nand flash array memo ry. it is accessed by issuing ot p access command(65h) instead of a flash block address (fba) command. after being accessed with the otp access command, the cont ents of otp memory area are loaded using the same operations as a normal load operation to the nand flash array memory (see section 3.6 for more information). to exit the otp access mode following an otp block load operation, a cold-, warm-, hot-, or nand flash core reset operation is per- formed. otp block read operation flow chart note : 1) fba(nand flash block address) could be omitted or any address. 2) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start wait for int register add: f241h dq[15]=int write 0 to interrupt register 2) add: f241h dq=0000h write ?fpa, fsa? of flash add: f107h dq=fpa, fsa otp reading completed write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int write ?otp access? command add: f220h dq=0065h write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc low to high transition otp exit host reads data from dataram do cold/warm/hot /nand flash core reset write ?fba? of flash 1) add: f100h dq=fba write 0 to interrupt register 2) add: f241h dq=0000h
onenand1gb(KFG1G16Q2C-xebx) flash memory - 98 - 3.14.2 otp block program operation an otp block program operation accesses the otp area and programs c ontent from the dataram on-chip buffer to the designated pag e(s) of the otp. a memory location in the otp area can be programmed only one time (no erase operation permitted). the otp area is programmed using the same sequence as normal progr am operation after being accessed by the command (see section 3.8 for more information). programming the otp area ? issue the otp access command ? write data into the dataram (data can be input at anytime between the "start" and "write program" commands ? issue a flash block address (fba) which is unloc ked area address of nand flash array address map. ? issue a write program command to program the data from the dataram into the otp ? when the otp block programming is complete, do a cold-, warm-, hot-, nand flash core reset to exit the otp access mode.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 99 - otp block program operation flow chart note : 1) fba(nand flash block address) could be omitted or any address. 2) data input could be done anywhere between "start" and "write program command". 3) fba should point the unlocked area address among nand flash array address map. 4) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 write ?fba? of flash 1) add: f100h dq=fba start data input write ?otp access? command add: f220h dq=0065h write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write data into dataram 2) add: dp dq=data-in otp programming completed write program command dq=0080h or 001ah completed? wait for int register low to high transition add: f241h dq[15]=int no add: f220h wait for int register add: f241h dq[15]=int write 0 to interrupt register 4) add: f241h dq=0000h low to high transition do cold/warm/hot otp exit automatically checked wait for int register low to high transition add: f241h dq[15]=int otp exit automatically otp l =0? yes no updated read controller status register add: f240h dq[10]=1(error) add: f200h dq=bsa, bsc write ?fba? of flash add: f100h dq=fba 3) read controller status register add: f240h dq[10]=0(pass) /nand flash core reset do cold/warm/hot /nand flash core reset write 0 to interrupt register 4) add: f241h dq=0000h update controller add: f240h status register dq[14]=1(lock), dq[10]=1(error)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 100 - 3.14.3 otp block lock operation even though the otp area can only be programmed once without erase capability, it can be locked when the device starts up to pr event any changes from being made. unlike the main area of the nand flash array memory, once the otp block is locked, it cannot be unlocked, for locking bit for both blocks lies in the same word of otp area. therefore, if otp block is lo cked prior to 1st block otp lo ck, 1st block otp cannot be locked. locking the otp programming to the otp area can be prevented by locking the ot p area. locking the otp area is accomplished by programming xxfch to 8th word of sector0 in page0 spare area in the otp block. at device power-up, this word location is checked and if xxfch is found, the otp l bit of the controller status register is set to "1", indicating the otp is locked. when the program operation finds that the stat us of the otp is locked, the dev ice updates the error bit of t he controller status register as "1" (fail). otp lock operation steps ? issue the otp access command ? fill data to be programmed into dataram (data can be input at anytime between the "start" and "write program" commands) ? write ' xxfch ' data into the 8th word of sector0 in page0 spare area of the dataram. ? issue a flash block address (fba) which is unloc ked area address of nand flash array address map. ? issue a program command to program the data from the dataram into the otp ? when the otp lock is complete, do a cold reset to exit the otp access mode and update otp lock bit[6]. ? otp lock bit[6] of the controller status register will be set to "1" and the otp will be locked.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 101 - otp block lock operation flow chart note : 1) fba(nand flash block address) could be omitted or any address. 2) data input could be done anywhere between "start" and "write program command". 3) fba should point the unlocked area address among nand flash array address map. 4) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start write ?fpa, fsa? of flash add: f107h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=0801h/0c01h write data into dataram 2) add: 8th word write program command dq=0080h or 001ah wait for int register low to high transition add: f241h dq[15]=int add: f220h write 0 to interrupt register 4) add: f241h dq=0000h automatically updated dq=xxfch in sector0/spare/page0 otp lock completed write ?fba? of flash add: f100h dq=fba 3) write ?otp access? command add: f220h dq=0065h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register 4) add: f241h dq=0000h do cold reset write ?fba? of flash 1) add: f100h dq=fba update controller add: f240h status register dq[6]=1(otp l )
onenand1gb(KFG1G16Q2C-xebx) flash memory - 102 - 3.14.4 1st block otp lock operation 1st block could be used as otp, for secured booting operation. 1st block otp can be accessed just as any other nand flash array blocks before it is locked, however, once 1st block is locked to be otp, 1st block otp cannot be erased or programmed. note that otp block can be locked freely after locking 1st block otp. locking the 1st block otp programming to the 1st block otp area can be prevented by lo cking the otp area. locking the otp area is accomplished by programming xxf3h to 8th word of sector0 in page0 spare area in the otp block. at device power-up, this word location is checked and if xxf3h is found, the otp bl bit of the controller status r egister is set to "1", indicating the 1st block is locked. when the program operation finds that the status of the 1st block is locked, the device updates the er ror bit of the controller status register as "1" (fail). 1st block otp lock operation steps ? issue the otp access command ? fill data to be programmed into dataram (data can be input at anytime between the "start" and "write program" commands) ? write ' xxf3h ' data into the 8th word of sector0 in page0 spare area of the dataram. ? issue a flash block address (fba) which is unloc ked area address of nand flash array address map. ? issue a program command to program the data from the dataram into the otp ? when the 1st block otp lock is complete, do a cold reset to exit the otp access mode and update 1st block otp lock bit[5]. ? 1st block otp lock bit[5] of the controller status regi ster will be set to "1" and the 1st block will be locked. even though the otp area can only be programmed once without erase capability, it can be locked when the device starts up to pr event any changes from being made. unlike other remaining main area of the nand flash array memory, once the 1st block otp is locked, it cannot be unlocked.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 103 - 1st block otp lock operation flow chart note : 1) fba(nand flash block address) could be omitted or any address. 2) data input could be done anywhere between "start" and "write program command". 3) fba should point the unlocked area address among nand flash array address map. 4) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start write ?fpa, fsa? of flash add: f107h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=0801h/0c01h write data into dataram 2) add: 8th word write program command dq=0080h or 001ah wait for int register low to high transition add: f241h dq[15]=int add: f220h write 0 to interrupt register 4) add: f241h dq=0000h automatically updated dq=xxf3h in sector0/spare/page0 1st block otp lock completed write ?fba? of flash add: f100h dq=fba 3) write ?otp access? command add: f220h dq=0065h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register 4) add: f241h dq=0000h do cold reset write ?fba? of flash 1) add: f100h dq=fba update controller add: f240h status register dq[5]=1(otp bl )
onenand1gb(KFG1G16Q2C-xebx) flash memory - 104 - 3.14.5 otp and 1st block otp lock operation otp and 1st block can be locked simultaneously, for lo cking bit lies in the same word of otp area. 1st block otp can be accessed just as any other nand flash array blocks before it is locked, however, once 1st block is locked to be otp, 1st block otp cannot be erased or programmed. also, otp area can only be programmed once without erase capability, it can be lo cked when the device starts up to prevent any changes from being made. locking the otp and 1st block otp programming to the otp area and 1st block ot p area can be prevented by locking the otp area. locking the otp area is accomplis hed by programming xxf0h to 8th word of sector0 in page0 spare area in the otp block. at device power-up, this word location is checked and if xxf0h is found, the otp l and otp bl bit of the controller status register is set to "1", indicating the otp and 1st block is locked. when the program operation finds that the status of the otp and 1st block is locked , the device updates the error bit of the controlle r status register as "1" (fail). otp and 1st block otp simultaneous lock operation steps ? issue the otp access command ? fill data to be programmed into dataram (data can be input at anytime between the "start" and "write program" commands) ? write 'xxf0h' data into the 8th word of sector0 in page0 spare area of the dataram. ? issue a flash block address (fba) which is unloc ked area address of nand flash array address map. ? issue a program command to program the data from the dataram into the otp ? when the 1st block otp lock is complete, do a cold reset to exit the otp access mode and update 1st block otp lock bit[5] and otp lock bit[6]. ? 1st block otp lock bit[5] and otp lock bit[6] of the c ontroller status register will be set to "1" and the otp and 1st block will be locked. even though the otp area can only be programmed once without erase capability, it can be locked when the device starts up to pr event any changes from being made. unlike other remaining main area of the nand flash array memory, once the otp block and the 1st block otp are locked, it cannot be unlocked.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 105 - otp and 1st block otp lock operation flow chart note : 1) fba(nand flash block address) could be omitted or any address. 2) data input could be done anywhere between "start" and "write program command". 3) fba should point the unlocked area address among nand flash array address map. 4) ?write 0 to interrupt register? step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start write ?fpa, fsa? of flash add: f107h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=0801h/0c01h write data into dataram 2) add: 8th word write program command dq=0080h or 001ah wait for int register low to high transition add: f241h dq[15]=int add: f220h write 0 to interrupt register 4) add: f241h dq=0000h automatically updated dq=xxf0h in sector0/spare/page0 write ?fba? of flash add: f100h dq=fba 3) write ?otp access? command add: f220h dq=0065h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register 4) add: f241h dq=0000h do cold reset write ?fba? of flash 1) add: f100h dq=fba otp and 1st block otp lock completed update controller add: f240h status register dq[6]=1(otp l ) dq[5]=1(otp bl )
onenand1gb(KFG1G16Q2C-xebx) flash memory - 106 - 3.15 dual operations the device has independent dual data buffers on-chip (except duri ng the boot load period) that enables higher performance read and pro- gram operation. 3.15.1 read-while-load operation this operation accelerates the read performance of the device by enabling data to be read out by the host from one dataram buff er while the other dataram buffer is being loaded with data from the nand flash array memory. the dual data buffer architecture provides the capability of ex ecuting a data-read operation from one of dataram buffers during a simulta- neous data-load operation from flash to the other buffer. simu ltaneous load and read operation to same data buffer is prohibite d. see sec- tions 3.6 and 3.7 for more information on load and read operations. if host sets fba, fsa, or fpa while loading into designated page, it will fail the internal l oad operation. address registers should not be updated until internal operation is completed. 3.15.2 write-while-program operation this operation accelerates the programming performance of the devic e by enabling data to be written by the host into one datara m buffer while the nand flash array memory is being programmed with data from the other dataram buffer. the dual data buffer architecture provides the capability of executing a data-write operation to one of dataram buffers during simultaneous data-program operation to flash from the other buffer. simultaneous program and write operation to same data buffer is prohib ited. see sec- tions 3.8 for more information on program operation. if host sets fba, fsa, or fpa while programming into designated p age, it will fail the internal program operation. address reg isters should not be updated until internal operation is completed. page a page b 1) data load 2) data load data buffer1 data buffer0 2) data read 3) data read 3) data load page a page b 2) program 3) program data buffer1 data buffer0 1) data write 2) data write 3) data write
onenand1gb(KFG1G16Q2C-xebx) flash memory - 107 - read while load diagram page b add we oe int 0~15 2) 2) page a 1) add_ reg int_ reg cmd_ reg cs_ reg data load _db0 data load _db1 data read _db0 * add_ reg int_ reg cmd_ reg add_ reg add_ reg db1 _add ld_ cmd read status db0 _add 0000h ld_ cmd flash dq 0~15 int_reg : interrupt register address add_reg : address register address flash_add : flash address to be loaded dbn_add : dataram address to be loaded cmd_reg : command register address ld_cmd : load command data load_dbn : load data from nand flash array to dataramn cs_reg : controller status register address data read_dbn : read data from dbn dbn_radd : dataram address to be read 1) data load _db0 db0_radd* data load _db1 _add 0000h flash _add
onenand1gb(KFG1G16Q2C-xebx) flash memory - 108 - write while program diagram page b add oe int 0~15 page a 1) we db0_wadd* add_ reg add_ reg int_ reg cmd_ reg cs_ reg int_ reg cmd_ reg data pgm _pageb dq 0~15 db0 _add flash _add 0000h pd_ cmd data write _db1 * db1 _add read status 0000h pd_ cmd data pgm _pagea add_reg : address register address dbn_add : dataram address to be programmed dbn_wadd : dataram address to be written data write_dbn : write data to dataramn flash_add : flash address to be programmed int_reg : interrupt register address cmd_reg : command register address pd_cmd : program command data pgm_pagea : program data from dataram to pagea cs_reg : controller status register address data write _db0 * db1_wadd* data pgm _pagea 2) add_ reg add_ reg flash _add data write _db0 * db0_wadd* data pgm _pageb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 109 - 3.16 ecc operation the onenand device has on-chip ecc with t he capability of detecting 2 bit errors and correcting 1-bit errors in the nand flash array mem- ory main and spare areas. as the device transfers data from a bufferram to the nand flash array memory page buffer for program operation, the device init iates a background operation which generates an error correction code (ecc) of 24bits for each sector main area data and 10bits for 2nd and 3rd word data of each sector spare area. during a load operation from the nand flash array memory page, t he on-chip ecc engine generates a new ecc. the 'load ecc result ' is compared to the originally 'program e cc' thus detecting the number and position of errors. single-bit error is corrected. ecc is updated by the device automatically. after a load operation, the host can determine whether there was error by reading t he 'ecc sta- tus register' (refer to section 2.8.26). error types are divided into 'no er ror', '1bit correctable error', and '2bit error uncorrectable error'. onenand supports 2bit edc even though 2bit erro r seldom or never occurs. hence, it is not recommended for host to read 'ecc sta tus reg- ister' for checking ecc error because the built-in error correction logic of onen and automatically corrects ecc error. when the device reads the nand flash array memory main and spare area data with an ecc operation, the device doesn't place the newly generated ecc for main and spare area into the buffer. instead it places the ecc which was generated and written during the pro gram oper- ation into the buffer. an ecc operation is also done during the boot loading operation. 3.16.1 ecc bypass operation in an ecc bypass operation, the device does not generate ecc as a background operation. the result does not indicate error posi tion (refer to the ecc result table). in a program operation the ecc code to nand flash array memory spare area is not updated. during a load operation, the on-chip ecc engine does not generate a new ecc internally. also the ecc status & result to regist ers are invalid. the error is not corrected and detected by itsel f, so that ecc bypass operation is not recommended for host. ecc bypass operation is set by the 9bit of syst em configuration 1 register (see section 2.8.19) ecc code and ecc result by ecc operation note : 1) pre-written ecc code : ecc code whic h is previously written to nand flas h spare area in program operation. operation program operation load operation ecc code update to nand flash array spare area ecc code at bufferram spare area ecc status & result update to registers 1bit error ecc operation update pre-written ecc code (1) loaded update correct ecc bypass not update pre-written code (1) loaded invalid not correct
onenand1gb(KFG1G16Q2C-xebx) flash memory - 110 - 3.17 invalid block operation invalid blocks are defined as blocks in t he device's nand flash array memo ry that contain one or more invalid bits whose reliab ility is not guaranteed by samsung. the information regarding the invalid block(s) is called the inva lid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the performance of valid bl ock(s) because it is isolated fr om the bit line and the common s ource line by a select transistor. the system design must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h bloc k address, is always fully guaranteed to be a valid block. due to invalid marking, during load operation for i ndentifying invalid block, a load error may occur. 3.17.1 invalid block identification table operation a system must be able to recognize invalid block(s) based on the original invalid block information and create an invalid block table. invalid blocks are identified by erasing all address locations in the nand flash array memory except locations where the invali d block(s) infor- mation is written prior to shipping. an invalid block(s) status is defined by the 1st word in the sp are area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffffh data at the 1st word of sector0. since the invalid block information is also erasable in most case s, it is impossible to recover the information once it has bee n erased. any intentional erase of the original inva lid block information is prohibited. the following suggested flow chart can be used to create an invalid block table.
onenand1gb(KFG1G16Q2C-xebx) flash memory - 111 - invalid block table creation flow chart 3.17.2 invalid block replacement operation within its life time, additional invalid blocks may develop with nand flash array memo ry. refer to the device's qualification r eport for the actual data. the following possible failure m odes should be considered to impl ement a highly reliable system. in the case of a status read failure after erase or program, a block replacement should be done. because program status failure during a page program does not affect the data of the other pages in the same block, a block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. block failure modes and countermeasures failure mode detection and countermeasure sequence erase failure status read after erase --> block replacement program failure status read after program --> block replacement single bit failure in load operation error correction by ecc mode of the device * start set block address = 0 check increment block address last block ? end no yes yes create (or update) no invalid block(s) table "ffffh" ? check "ffffh" at the 1st word of sector 0 of spare area in 1st and 2nd page
onenand1gb(KFG1G16Q2C-xebx) flash memory - 112 - referring to the diagram for further illustration, when an er ror happens in the nth page of block 'a' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'b' via data buffer0. then copy the nth page data of block 'a' in the data buffer1 to th e nth page of block 'b' or any free block. do not further era se or program block 'a' but instead complete the operation by creating an 'invalid block table' or other appropriate scheme. block replacement operation sequence data buffer1 of the device 1st block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 data buffer0 of the device 1 (assuming the nth page data is maintained)
onenand1gb(KFG1G16Q2C-xebx) flash memory - 113 - 4.0 dc characteristics 4.1 absolute maximum ratings note : 1) minimum dc voltage is -0.5v on input/ output pins. during transitions, this level should not fall to por level(typ. 1.5v). maximum dc voltage may overshoot to vcc+2.0v for periods <20ns. 2) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. 4.2 operating conditions voltage reference to gnd note : 1) vcc-core (or vcc) should reach the operating voltage level prior to or at the same time as vcc-io (or vccq). parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to + 2.45 v all pins v in -0.5 to + 2.45 temperature under bias extended t bias -30 to +125 c storage temperature t stg -65 to +150 c short circuit output current i os 5ma recommended operating temperature t a (extended temp.) -30 to +85 c t a (industrial temp.) -40 to +85 parameter symbol KFG1G16Q2C unit min typ. max supply voltage v cc- core / vcc 1.7 1.8 1.95 v v cc- io / vccq v ss 000v
onenand1gb(KFG1G16Q2C-xebx) flash memory - 114 - 4.3 dc characteristics note : 1) ce should be vih for rdy. iobe should be ?0? for int. 2) i cc active for host access 3) i cc active for internal operation. (without host access) 4) vccq is equivalent to vcc-io. parameter symbol test conditions rms value unit min typ max input leakage current i li v in =v ss to v cc , v cc =v ccmax - 1.0 - + 1.0 a output leakage current i lo v out =v ss to v cc , v cc =v ccmax , ce or oe =v ih (note 1) - 1.0 - + 1.0 a active asynchronous read current (note 2) i cc1 ce =v il , oe =v ih -815ma active burst read current (note 2) i cc2r ce =v il , oe =v ih , we =v ih 66mhz - 15 25 ma 83mhz - 20 30 ma 1mhz - 3 4 ma active burst write current (note 2) i cc2w ce =v il , oe =v ih, we =v il 66mhz - 15 25 ma 83mhz - 20 30 ma 1mhz - 3 4 ma active asynchronous write current (note 2) i cc3 ce =v il , oe =v ih -815ma active load current (note 3) i cc4 ce =v il , oe =v ih , we =v ih -3040ma active program current (note 3) i cc5 ce =v il , oe =v ih , we =v ih -2530ma active erase current (note 3) i cc6 ce =v il , oe =v ih , we =v ih -2025ma multi block erase current (note 3) i cc7 ce =v il , oe =v ih , we =v ih , 64blocks - 20 25 ma standby current i sb ce = rp =v cc 0.2v - 10 50 a input low voltage v il --0.5-0.4v input high voltage (note 4) v ih -v ccq -0.4 - v ccq +0.4 v output low voltage v ol i ol = 100 a ,v cc =v ccmin , v ccq =v ccqmin --0.2v output high voltage v oh i oh = -100 a , v cc =v ccmin , v ccq =v ccqmin v ccq -0.1 - - v
onenand1gb(KFG1G16Q2C-xebx) flash memory - 115 - 5.0 ac characteristics 5.1 ac test conditions 5.2 device capacitance capacitance (t a = 25 c, v cc = 1.8v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. 5.3 valid block characteristics note : 1) the device may include invalid blocks when first shipped. additional inva lid blocks may develop while being used. the number of valid blo cks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks. 2) the 1st block, which is placed on 00h bl ock address, is guaranteed to be a valid block up to 1k program/erase cycles with 1b it/512byte ecc. parameter value (66mhz) value (83mhz) input pulse levels 0v to v cc 0v to v cc input rise and fall times clk 3ns 2ns other inputs 5ns 2ns input and output timing levels v cc /2 v cc /2 output load c l = 30pf c l = 30pf item symbol test condition KFG1G16Q2C unit min max input capacitance c in1 v in =0v - 10 pf control pin capacitance c in2 v in =0v -10pf output capacitance c out v out =0v - 10 pf int capacitance c int v out =0v - 10 pf parameter symbol min typ. max unit valid block number n vb 1004 - 1024 blocks 0v v cc v cc /2 v cc /2 input pulse and test point input & output test point output load device under te s t * c l = 30pf including scope and jig capacitance
onenand1gb(KFG1G16Q2C-xebx) flash memory - 116 - 5.4 ac characteristics for synchronous burst read see timing diagrams 6.1, 6.2 and 6.3. note : 1) if oe is disabled at the same time or before ce is disabled, the output will go to high-z by toez. if ce is disabled at the same time or before oe is disabled, the output will go to high-z by tcez. if ce and oe are disabled at the same time, the output will go to high-z by toez. 2) it is the following clock of address fetch clock. parameter symbol 66mhz 83mhz unit min max min max clock clk166183mhz clock cycle t clk 15 - 12 - ns initial access time t iaa - 70 - 70 ns burst access time valid clock to output delay t ba -11- 9ns avd setup time to clk t avds 5-4-ns avd hold time from clk t avdh 2-2-ns address setup time to clk t acs 5-4-ns address hold time from clk t ach 6-6-ns data hold time from next clock cycle t bdh 3-2-ns output enable to data t oe - 20 - 20 ns ce disable to output & rdy high z t cez 1) - 20 - 20 ns oe disable to output high z t oez 1) - 15 - 15 ns ce setup time to clk t ces 6 - 4.5 - ns clk high or low time t clkh/l t clk /3 - 5 - ns clk 2) to rdy valid t rdyo -11- 9ns clk to rdy setup time t rdya -11- 9ns rdy setup time to clk t rdys 4-3-ns ce low to rdy valid t cer - 15 - 15 ns
onenand1gb(KFG1G16Q2C-xebx) flash memory - 117 - 5.5 ac characteristics for asynchronous read see timing diagrams 6.5, 6.6, 6.7 and 6.8. note : 1) if oe is disabled at the same time or before ce is disabled, the output will go to high-z by toez. if ce is disabled at the same time or before oe is disabled, the output will go to high-z by tcez. if ce and oe are disabled at the same time, the output will go to high-z by toez. these parameters are not 100% tested. 5.6 ac characteristics for warm reset (rp ), hot reset and na nd flash core reset note : 1) these parameters are tested based on int bit of interrupt register. because the time on int pin is related to the pull-up an d pull-down resistor value. 2) the device may reset if trp < trp min(200ns), but this is not guaranteed. parameter symbol KFG1G16Q2C unit min max access time from ce low t ce -76ns asynchronous access time from avd low t aa -76ns asynchronous access time from address valid t acc -76ns read cycle time t rc 76 - ns avd low time t avdp 12 - ns address setup to rising edge of avd t aavds 7-ns address hold from rising edge of avd t aavdh 6-ns output enable to output valid t oe -20ns ce disable to output & rdy high z 1) t cez -20ns oe disable to output high z 1) t oez -15ns ce low to rdy valid t cer -15ns we disable to avd enable t wea 15 - ns parameter symbol min max unit rp & reset command latch to bootram access tready1 (bootram) -5 s rp & reset command latch(during load routines) to int high (note1) tready2 (nand flash array) -10 s rp & reset command latch(during program routines) to int high (note1) tready2 (nand flash array) -20 s rp & reset command latch(during erase routines) to int high (note1) tready2 (nand flash array) - 500 s rp & reset command latch(not during internal routines) to int high (note1) tready2 (nand flash array) -10 s rp pulse width (note2) trp 200 - ns
onenand1gb(KFG1G16Q2C-xebx) flash memory - 118 - 5.7 ac characteristics for asynchronous write see timing diagrams 6.9. 5.8 ac characteristics for burst write operation see timing diagrams 6.10 and 6.11. note : 1) target clock frequency is 83mhz parameter symbol min max unit we cycle time t wc 70 - ns address setup time t awes 0 - ns address hold time t ah 30 - ns data setup time t ds 25 - ns data hold time t dh 0 - ns ce setup time t cs 0 - ns ce hold time t ch 0 - ns we pulse width t wpl 40 - ns we pulse width high t wph 30 - ns ce disable to output & rdy high z t cez -20ns parameter symbol 66mhz 83mhz unit min max min max clock clk 1) 166183mhz clock cycle t clk 15 - 12 - ns avd setup to clk t avds 5-4-ns avd hold time from clk t avdh 2-2-ns address setup time to clk t acs 5-4-ns address hold time from clk t ach 6-6-ns data setup time to clk t wds 5-4-ns data hold time from clk t wdh 2-2-ns we setup time to clk t wes 5-4-ns we hold time from clk t weh 3-3-ns clk high or low time t clkh/l t clk /3 - 5 - ns ce high pulse width t cehp 10 - 10 - ns clk to rdy valid t rdyo -11- 9ns clk to rdy setup time t rdya -11- 9ns rdy setup time to clk t rdys 4 - 3 -ns ce low to rdy valid t cer -15-15ns clock to ce disable t ceh 2t clk - 4.5 2 t clk - 4.5 ns ce setup time to clk t ces 6-4.5-ns ce disable to output & rdy high z t cez -20-20ns
onenand1gb(KFG1G16Q2C-xebx) flash memory - 119 - 5.9 ac characteristics for load /program/erase performance see timing diagrams 6.12, 6.13, and 6.14 note : 1) these parameters are tested based on int bit of interrupt register. because the time on int pin is related to the pull-up an d pull-down resistor value. 2) spare load time is little bit less than sector load time. 3) spare program time is same as sector program time. 4) 2/3 sector load/program time is between sector load/progrma time and page load/program time. 5.10 ac characteristics for int auto mode see timing diagrams 6.20 5.11 ac characteristics for sy nchronous burst block read see timing diagrams 6.4 parameter symbol min typ max unit spare load time(note 1, note2) t rd1 -2335 s sector load time(note 1) page load time(note 1) t rd2 -3045 s spare program time(note 1, note3) t pgm1 - 205 720 s sector program time(note 1) page pogram time(note 1) t pgm2 - 220 750 s otp access time(note 1) t otp - 500 700 ns lock/unlock/lock-tight (note 1) t lock - 500 700 ns all block unlock time (note 1) t abu -23 s erase suspend time(note 1) t esp - 400 500 s erase resume time(note 1) 1 block t ers1 -1.52ms 2~64 blocks t ers2 46ms number of partial program cycles in the page (including main and spare area) nop - - 4 cycles block erase time (note 1) 1 block t bers1 -1.52ms 2~64 blocks t bers2 - 46ms multi block erase verify read time(note 1) t rd3 - 70 100 s parameter symbol min max unit command input to int low t wb - 200 ns parameter symbol typ. max unit int low period during synch burst block read t intl 1-us
onenand1gb(KFG1G16Q2C-xebx) flash memory - 120 - 6.0 timing diagrams 6.1 8-word linear burst read mode with wrap around see ac characteristics table 5.4 6.2 continuous linear burst read mode with wrap around see ac characteristics table 5.4 t ces t avds t avdh t acs t ach t iaa t ba t bdh t clk ce clk avd oe dq0-dq15 a0-a15 d6 d7 d0 d1 d2 d3 d7 t rdya t oe brwl=4 t cez t oez d0 t clkh t clkl t rdyo t cer hi-z rdy t rdys hi-z 0 -1 1 2 3 4 t ces t avds t avdh t acs t ach t iaa t ba t bdh t clk hi-z ce clk avd oe dq0-dq15 rdy a0-a15 t rdys da da+1 da+2 da+3 da+4 da+5 da+n t rdya t oe brwl=4 t cez t oez da+n+1 hi-z t rdyo t cer 0 -1 1 2 3 4
onenand1gb(KFG1G16Q2C-xebx) flash memory - 121 - 6.3 synchronous burst block read operation timing see ac characteristics table 5.4 and 5.7. we ce clk t ds t wpl t cs t wph t wc fpa fba oe int t ch t cs avd v il t dh t rd2 sbbrcd fpc dq0-dq15 hi-z d0 d1 d2 rdy note : asynchronous write was used in this timi ng diagram. synchronous write is also possible. 1)aa = address of address register ca = address of command register sbbrcd = synchronous burst block read command fba = flash block address fpa = flash page address bsa = bufferram sector address fpc= number of flash page to be read (3pages ~ 64pages) . . . . . . . . . . . . . . . . . . . . . . . . aa aa a0-a15 t aavdh t aavds ca . . . start add aa aa bsa
onenand1gb(KFG1G16Q2C-xebx) flash memory - 122 - 6.4 synchronous burst block read timing see ac characteristics table 5.11 case 1 : bl=1k word synchronous burst block read start page address setting number of pages synchronous burst block read command a0~ clk rdy high-z high-z int: indicator for dataram?s status (ready=high, busy=low) rdy: indicator for latency of sync burst block read burst length: 4, 8, 16, 32, 1k word, and conti nuous synchronous burst block read are available. a1~a4: for the fixed number of words linear burst bloc k read, a1~a4 are start address of the each dataram. for detailed timing diagram, refer to chapter 6.3 we must be set high throughout the operation. a15 a1 a2 a3 a4 int . . . . . . . . . . .. . . . . . . . . . . . we oe avd high . . . . . . high . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . 1st page out 2nd page out 3rd page out 4th page out dq0~ dq15 high-z . . . . . . . . . . .. . . . . . ce . . high . . . . . . . . .. . . . case 1 : bl=1k word synchronous burst block read t intl
onenand1gb(KFG1G16Q2C-xebx) flash memory - 123 - case 2 : host reads int bit for ready/busy state indicator 1st burst data nth burst data start page address setting number of pages synchronous burst block read command ce clk rdy high-z nt bit : indicator for dataram?s status (ready=1, busy=0) rdy: indicator for latency of sync burst block read burst length: 4, 8, 16, 32, 1k word sy nchronous burst block read are available. a1-1 ~ a1-n: address where each burst data initiates, a nd this may differ for different settings of bsa and bl. n can be calculated by 1024w / bl. therefore, for above case, bsa=0200h and bl=8word. so that n=128, a1-1=0200h, a1-2=0208h ... a1-128=05f8h. we must be set high throughout the operation. f241h a1-1 a1-n . . . .. . . . . . . . . . . . . . we oe avd high high . . . . . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . dq[15] polling f241h dq[15] polling f241h dq[15] polling . high-z high case 2 : host reads int bit for ready/busy state indicator . . . .. . . . a0~ a15 dq0~ dq15 . .
onenand1gb(KFG1G16Q2C-xebx) flash memory - 124 - 6.5 asynchronous read (va transition before avd low) see ac characteristics table 5.5 note : va=valid read address, rd=read data. 6.6 asynchronous read (va transition after avd low) see ac characteristics table 5.5 note : va=valid read address, rd=read data. t oe va valid rd t ce t oez ce oe we a0-a15 clk v il avd hi-z hi-z rdy t avdp t aavdh dq0-dq15 t cez t oe va valid rd t oez ce oe we a0-a15 clk v il avd t aa hi-z hi-z rdy t avdp t aavdh dq0-dq15 t wea t cez
onenand1gb(KFG1G16Q2C-xebx) flash memory - 125 - 6.7 asynchronous read (va and avd transition after ce low) see ac characteristics table 5.5 note : va=valid read address, rd=read data. 6.8 asynchronous read (avd is tied to ce ) see ac characteristics table 5.5 note : va=valid read address, rd=read data. t oe va valid rd t oez ce oe we a0-a15 t acc clk v il avd t aavds hi-z hi-z rdy t avdp t aavdh dq0-dq15 t wea t cez t oe va valid rd t ce t oez ce oe we a0-a15 t acc clk v il hi-z hi-z rdy t rc dq0-dq15 t cez
onenand1gb(KFG1G16Q2C-xebx) flash memory - 126 - 6.9 asynchronous write see ac characteristics table 5.7 note : va=valid read address, wd=write data ce we oe rp a0-a15 t cs dq0- valid wd t ds rdy va valid wd t wpl t wph t wc t dh t awes va t ah hi-z hi-z clk v il t ch t cs dq15
onenand1gb(KFG1G16Q2C-xebx) flash memory - 127 - 6.10 8-word linear burst write m ode see ac characteristics table 5.8 t ces t avds t avdh t acs t ach t rdyo t wdh t wds t clk hi-z ce clk avd oe rdy t rdys t rdya a0~ a15 t cer t clkh t clkl hi-z t cer we t wes t weh t ceh -101234 brwl = 4 dq0~ dq15 d0 d1 d2 d3 d4 d5 d7 t cez
onenand1gb(KFG1G16Q2C-xebx) flash memory - 128 - 6.11 start initial burst write operation see ac characteristics table 5.8 t ces t avds t avdh t acs t ach t rdyo t wdh t wds t clk hi-z ce clk avd oe rdy t rdys t rdya t cer t clkh t clkl t cer we t wes t weh t ceh -1 0 1 2 3 4 brwl = 4 t cez t cehp brwl = 4 a0~ a15 dq0~ dq15 d0 d0
onenand1gb(KFG1G16Q2C-xebx) flash memory - 129 - 6.12 load operation timing see ac characteristics tables 5.7 and 5.9 note : 1) aa = address of address register ca = address of command register lcd = load command lma = address of memory to be loaded ba = address of bufferram to load the data bd = program data sa = address of status register 2) ?in progress? and ?complete? refer to status register 3) status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. load command sequence a0:a15 we ce clk t ds t dh t ch t wpl t cs t wph t wc ca ba ba lcd lma aa dq0-dq15 oe read data v il da da+1 t ah t awes int t ch t cs t rd1 or trd2
onenand1gb(KFG1G16Q2C-xebx) flash memory - 130 - 6.13 program operation timing see ac characteristics tables 5.7 and 5.9 note : 1) aa = address of address register ca = address of command register pcd = program command pma = address of memory to be programmed ba = address of bufferram to load the data bd = program data sa = address of status register aa* = address of start address1 register(for flash block address) pmb = dfs & fba(flash block address) of memory to be programmed next time 2) ?in progress? and ?complete? refer to status register 3) status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. program command sequence (last two cycles) read status data a0:a15 we ce clk t ds t dh t ch t wpl t cs t wph t wc sa in progress complete aa dq0-dq15 oe v il ba ca pcd pma bd t ah t awes t ch t ch t cs t cs t pgm1 or tpgm2 sa aa* pmb int
onenand1gb(KFG1G16Q2C-xebx) flash memory - 131 - 6.14 block erase operation timing see ac characteristics tables 5.7 and 5.9 note : 1) aa = address of address register ca = address of command register ecd = erase command ema = address of memory to be erased sa = address of status register aa* = address of start address1 register(for flash block address) pmb = dfs & fba(flash block address) of memory to be programmed next time 2) ?in progress? and ?complete? refer to status register 3) status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. erase command sequence (last two cycles) read status data a0:a15 we ce t ds t dh t ch ca sa sa in progress complete ecd ema aa dq0-dq15 oe t wpl t cs t wph t wc clk v il t ah t awes int t ch t cs t bers1 aa * pmb
onenand1gb(KFG1G16Q2C-xebx) flash memory - 132 - 6.15 cold reset timing note : 1) bootcode copy operation starts 400us later than por activation. the system power should reach 1.7v after por tri ggering level(typ. 1.5v) within 400us for valid boot code data. 2) 1k bytes bootcode copy takes typically 500us(max. 2ms) from sector0 and sector1/page0/block0 of nand flash array to bootram. host can read bootcode in bootram(1k bytes) after bootcode copy completion. 3) int register goes ?low? to ?high? on the condition of ?bootcode-copy done? and rp rising edge. if rp goes ?low? to ?high? before ?bootcode-copy done?, int register goes to ?low? to ?high? as soon as ?bootcode-copy done? system power sleep bootcode copy idle bootcode - copy done 3) 2) rp int onenand operation 0 (default) 1 iobe bit 1 (default) intpol bit high-z 1) int bit 0 (default) 1 por triggering level
onenand1gb(KFG1G16Q2C-xebx) flash memory - 133 - 6.16 warm reset timing see ac characteristics table 5.6 note : 1) the status which can accept any register based operation(load, program, erase command, etc). 2) the status where reset is ongoing. 3) the status allows only bootram(bl1) read operation for boot sequence.(refer to 7.2.2 boot sequence) 4) to read bl2 of boot sequence, host should wait int until becomes ready. and then, host can issue load command. (refer to 7.2.2 boot sequence, 7.1 methods of determing interrupt status) ce , oe rp t rp t ready1 rdy int high-z high-z t ready2 idle 1) operation status reset ongoing 2) bootram access 3) idle 1) int bit polling 4) bit
onenand1gb(KFG1G16Q2C-xebx) flash memory - 134 - 6.17 hot reset timing see ac characteristics table 5.6 note : 1) internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferram data are kept unchanged after warm/hot reset operations. 2) reset command : command based reset or register based reset 3) bp(boot partition): bootram area [0000h~01ffh, 8000h~800fh] 4) 00f0h for bp, and 00f3h for f220h avd bp(note 3) int a0~a15 we ce or f220h rdy operation or idle onenand reset idle onenand operation high-z dq0~dq15 00f0h or 00f3h 4) oe t ready 2 bit
onenand1gb(KFG1G16Q2C-xebx) flash memory - 135 - 6.18 nand flash core reset timing see ac characteristics table 5.6 6.19 data protection ti ming during power down the device is designed to offer prot ection from any involuntary program /erase during power-transitions. rp pin provides hardware protection and is recomended to be kept at v il before vcc drops to 1.5v avd ce f220h rdy operation or idle nand flash core reset idle onenand operation high-z 00f0h a0~a15 dq0~dq15 int we oe t ready 2 bit v cc rp onenand logic reset & nand array write protected int onenand operation typ. 1.5v 0v
onenand1gb(KFG1G16Q2C-xebx) flash memory - 136 - 6.20 int auto mode see ac characteristics table 5.10 note : int pin polarity is based on ?iobe=1 and int pol=1 (default)? setting write command into command register int will automatically turn to busy state int will automatically turn back to ready state when designated operation is completed. int pin int bit twb we dq cmd . . . . . . . . . . . . .
onenand1gb(KFG1G16Q2C-xebx) flash memory - 137 - 7.0 technical and application notes from time-to-time supplemental technical information and application notes pertai ning to the design and operation of the device in a system are included in this section. contact your samsung repr esentative to determine if additional notes are available. 7.1 methods of determ ining interrupt status there are two methods of determining interrupt status on the onen and. using the int pin or monitoring the interrupt status regi ster bit. the onenand int pin is an output pin function used to notify the host when a command has been completed. in ?cache read?, ?sync hro- nous burst block read?, int pin notifies that only trasferring from dataram to page buffer is completed. this provides a hardwa re method of signaling the completion of a program, erase, or load operation. in its normal state, the int pin is high if the int polarity bit is default. in case of normal int mode, before a command is w ritten to the com- mand register, the int bit must be written to '0' so the int pi n transitions to a low state indicating start of the operation. in case of ?int auto mode?, int bit is written to ?0? automatic ally right after command issued. upon comp letion of the command operation by the onen and?s inter- nal controller, int returns to a high state. int pin is a dq-type output allowing two int outputs to be or-tied together. refer to section 2.8 for additional information ab out int. at previ- ous 1gb onenand, int pin operates as an open-drain type. but at cu rrent 1gb b-die onenand, int pin operates as a dq-type which has faster responsiveness than open drain type. although dq-type int pin is connected to pull-up resi stor, dq-type int pin will not be affected by the resistor. int can be implemented by tying int to a host gpio or by cont inuous polling of the interrupt status register. int type (mono) general operation dq type
onenand1gb(KFG1G16Q2C-xebx) flash memory - 138 - 7.1.1 the int pin to a host general purpose i/o int can be tied to a host gpio to detect the risi ng edge of int, signaling the end of a command operation. this can be configured to operate either synchronously or asynchronously as s hown in the diagrams below. synchronous mode using the int pin when operating synchronously, int is tied directly to a host gpio. rdy could be conneceted as one of following guides. asynchronous mode using the int pin when configured to operate in an asynchronous mode, ce and avd of the onenand are tied to ce of the host. clk is tied to the host vss (ground). rdy is not connected. oe of the onenand and host are tied together and int is tied to a gpio. int command host onenand rdy(wait) oe clk ce rdy oe clk ce avd gpio int host onenand oe clk ce rdy oe clk ce avd gpio int handshaking mode non-handshaking mode host onenand oe vss ce rdy oe clk ce avd gpio int
onenand1gb(KFG1G16Q2C-xebx) flash memory - 139 - 7.1.2 polling the interrupt register status bit an alternate method of determining the end of an operation is to continuously monitor the interrupt status register bit instead of using the int pin. when using interrupt register instead of int pin, int pin is re commended to float to avoid power consumption at iobe=0(disable) . this can be configured in either a synchronous mode or an asynchronous mode. synchronous mode using interrupt status register bit polling when operating synchronously, ce and avd of the onenand are tied to ce of the host, clk, oe , and dq pins on the host and onenand are tied together. rdy could be c onnected as one of following guides. asynchronous mode using interrupt status register bit polling when configured to operate in an asynchronous mode, ce and avd of the onenand are tied to ce of the host. clk is tied to the host vss (ground). rdy is not connected. oe and dq of the onenand and host are tied together. int command host onenand rdy(wait) oe clk ce rdy oe clk ce avd dq dq host onenand oe clk ce rdy oe clk ce avd dq dq handshaking mode non-handshaking mode host onenand n.c oe ce rdy oe clk ce avd dq dq vss
onenand1gb(KFG1G16Q2C-xebx) flash memory - 140 - 7.2 boot sequence one of the best features onenand has is that it can be a booting device itself since it contains an internally built-in boot lo ader despite the fact that its core architecture is based on nand flash. thus , onenand does not make any additi onal booting device necessary for a system, which imposes extra cost or ar ea overhead on the overall system. as the system power is turned on, the boot code originally stored in nand flash array is moved to bootram automatically and the n fetched by cpu through the same interface as sram?s or nor flash?s if the size of the boot code is less than 1kb. if its size is larger than 1kb and less than or equal to 3kb, only 1kb of it can be moved to bootram automatically and fetched by cpu, and the rest of it can be l oaded into one of the datarams whose size is 2kb by load command and cpu can take it from the dataram after finishing the code-fetching jo b for bootram. if its size is larger than 3kb, the 1kb portion of it can be moved to bootram automatically and fetched by cpu, and it s remaining part can be moved to dram through two datarams using dual buffering and taken by cpu to reduce cpu fetch time. a typical boot scheme usually used to boot the system with onena nd is explained at partition of nand flash array and onenand bo ot sequence. in this boot scheme, boot code is comprised of bl1, w here bl stands for boot loader, bl2, and bl3. moreover, the size of the boot code is larger than 3kb (the 3rd case above). bl1 is called primary boot loader in other words. here is the table of detai led explanations about the function of each boot loader in this specific boot scheme. 7.2.1 boot loaders in onenand boot loaders in onenand nand flash array of onenand is di vided into the partitions as described at partit ion of nand flash array to show where each com ponent of code is located and how much portion of the overall nand flas h array each one occupies. in ad dition, the boot sequence is liste d below and depicted at boot sequence. 7.2.2 boot sequence boot sequence : 1. power is on bl1 is loaded into bootram 2. bl1 is executed in bootram bl2 is loaded into dram through two datarams using dual buffering by bl1 3. bl2 is executed in dram os image is loaded into dram through two datarams using dual buffering by bl2 4. os is running boot loader description bl1 moves bl2 from nand flash array to dr am through two datarams using dual buffering bl2 moves os image (or bl3 optionally) from nand flash array to dram through two datarams using dual buffering bl3 (optional) moves or writes the image through usb interface
onenand1gb(KFG1G16Q2C-xebx) flash memory - 141 - partition of nand flash array note : step 2 and step 3 can be copied into dram through two datarams using dual buffering onenand boot sequence reservoir file system os image nbl3 nbl2 nbl1 partition 6 block 162 block 2 block 1 block 0 partition 5 sector 0 sector 1 sector 2 sector 3 page 63 page 62 page 2 page 1 page 0 bl2 partition 4 partition 3 reservoir file system os image bl3 bl2 bl1 partition 6 block 162 block 2 block 1 block 0 partition 5 sector 0 sector 1 sector 2 sector 3 page 63 page 62 page 2 page 1 page 0 partition 4 partition 3 : : bl1 block 1023 reservoir file system os image bl2 bl1 os image bl 2 nand flash array onenand dram internal bufferram data ram 1 data ram 0 boot ram(bl 1) step 1 step 2 step 3
onenand1gb(KFG1G16Q2C-xebx) flash memory - 142 - 8.0 package dimensions 1gb product (KFG1G16Q2C) 0.10 max 0.45 0.05 0.32 0.05 0.9 0.10 bottom view top view a c e b d f 0.80x9=7.20 a 0.80x11=8.80 63- ? 0.45 0.05 g 4.40 0 . 8 0 b 0.20 m a b ? (datum a) (datum b) 2 543 1 6 3.60 #a1 index h 10.00 0.10 13.00 0.10 #a1 13 .00 0.10 0 . 8 0 10.00 0.10 13.00 0.10

▲Up To Search▲

Price & Availability of KFG1G16Q2C

	To Download KFG1G16Q2C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .